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Firmware for PCB CPLD with designator U39U31. Second CPLD Device in Chain: LCMX02-1200HC640HC
Feature Summary
- Power Management
- JTAG routing
- LED...
Firmware Revision and supported PCB Revision
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Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
---|---|---|---|---|
MIO13 | out | 36 | 1.8V_CPLD | output to drive gate of MOSFET transistor for Status-LED |
MODE0 | in | 35 | 1.8V_CPLD | ZynqMP boot mode pin 0 |
PG_VCCRF | in | 34 | 1.8V_CPLD | Power Good input from PWR_PRE |
SRST_B | 33 | 1.8V_CPLD | ||
PROG_B | 32 | 1.8V_CPLD | ||
PG_GR2 | in | 31 | 1.8V_CPLD | Power control input from PWR_PS and PWR_DDR |
MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmit pin |
MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin |
FPGA_IO0 | inout | 27 | 1.8V_CPLD | FPGA GPIO |
FPGA_IO1 | inout | 26 | 1.8V_CPLD | FPGA GPIO |
EN_PS_PL | out | 14 | 3.3V_CPLD | Power enable for PWR_CORE , PWR_PS and PWR_GT |
EN_GR1 | out | 15 | 3.3V_CPLD | Power enable for PWR_GT and PWR_PS |
EN_RF_ADC | out | 16 | 3.3V_CPLD | Power enable for PWR_ADC |
PG_RF_DAC | in | 17 | 3.3V_CPLD | Power control input from PWR_DAC |
EN_VCCRF | out | 18 | 3.3V_CPLD | Power enable for PWR_PRE |
EN_GR2 | out | 19 | 3.3V_CPLD | Power enable for PWR_DDR , PWR_GT and PWR_PS |
PG_PS_PL | in | 20 | 3.3V_CPLD | power control input from PWR_CORE , PWR_GT and PWR_PS |
PG_GR1 | in | 21 | 3.3V_CPLD | Power control input from PWR_GT and PWR_PS |
PG_RF_ADC | in | 23 | 3.3V_CPLD | Power control input from PWR_ADC |
EN_RF_DAC | out | 24 | 3.3V_CPLD | Power enable for PWR_DAC |
MODE2 | in | 2 | 1.8V_CPLD | ZynqMP boot mode pin 2 |
MODE1 | in | 3 | 1.8V_CPLD | ZynqMP boot mode pin 1 |
POR_B | out | 4 | 1.8V_CPLD | Power-On reset signal |
MODE3 | in | 5 | 1.8V_CPLD | ZynqMP boot mode pin 3 |
INIT_B | in | 7 | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal |
F_TDI | out | 8 | 1.8V_CPLD | JTAG ZynqMP |
F_TMS | out | 9 | 1.8V_CPLD | JTAG ZynqMP |
F_TCK | out | 10 | 1.8V_CPLD | JTAG ZynqMP |
F_TDO | in | 11 | 1.8V_CPLD | JTAG ZynqMP |
DONE | in | 12 | 1.8V_CPLD | FPGA PL configuration done indicator / currently_not_used |
JTAG_TDO | out | 48 | 3.3V_CPLD | JTAG_B2B |
JTAG_TDI | in | 47 | 3.3V_CPLD | JTAG_B2B |
JTAG_TCK | in | 45 | 3.3V_CPLD | JTAG_B2B |
JTAG_TMS | in | 44 | 3.3V_CPLD | JTAG_B2B |
CPLD_IO0 | 43 | |||
CPLD_IO1 | 3.3V_CPLD | |||
CPLD_JTAGEN | in | 41 | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
CPLD_IO2 | 3.3V_CPLD | |||
CPLD_IO3 | 3.3V_CPLD | |||
RESETN | in | 37 | 3.3V_CPLD | Reset pin of CPLD (Active low) |
Functional Description
JTAG
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