Overview

Firmware for RFSoC module CPLD with designator U31: LCMX02-640HC

Feature Summary

  • Firmware
  • Power Management
  • JTAG routing
  • Boot Mode
  • User IO
  • LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/PulldownBank PowerDescription
PWR_STATUSout36NONE1.8V_CPLDOutput for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0)
MODE0out35NONE1.8V_CPLDZynqMP boot mode pin 0
MODE1out3NONE1.8V_CPLDZynqMP boot mode pin 1
MODE2out2NONE1.8V_CPLDZynqMP boot mode pin 2
MODE3out5NONE1.8V_CPLDZynqMP boot mode pin 3
PG_V_1V8_RFin34NONE1.8V_CPLD
  • PG_VCCRF is the old name for PCB REV02 and REV01.
  • Power Good input from PWR_PRE
PG_V_1V8_IOin31NONE1.8V_CPLD
  • PG_GR2 is the old name for PCB REV02 and REV01.
  • Power control input from PWR_PS and PWR_DDR
PG_0V85in20NONE3.3V_CPLD
  • PG_PS_PL is the old name for PCB REV02 and REV01.
  • power control input from PWR_CORE , PWR_GT and PWR_PS
PG_V_1V2in21NONE3.3V_CPLD
  • PG_GR1 is the old name for PCB REV02 and REV01.
  • Power control input from PWR_GT and PWR_PS
PG_V_3V3_IOin23NONE3.3V_CPLD
  • PG_RF_ADC is the old name for PCB REV02 and REV01.
  • Power control input from PWR_ADC
PG_V_0V925_RFin17NONE3.3V_CPLD
  • PG_RF_DAC is the old name for PCB REV02 and REV01.
  • Power control input from PWR_DAC
EN_V_3V3_IOout18NONE3.3V_CPLD
  • EN_VCCRF is the old name for PCB REV02 and REV01.
  • Power enable for PWR_PRE
EN_V_1V8_IOout19NONE3.3V_CPLD
  • EN_GR2 is the old name for PCB REV02 and REV01.
  • Power enable for PWR_DDR , PWR_GT and PWR_PS
EN_0V85out14NONE3.3V_CPLD
  • EN_PS_PL is the old name for PCB REV02 and REV01.
  • Power enable for PWR_CORE , PWR_PS and PWR_GT
EN_V_1V2out15NONE3.3V_CPLD
  • EN_GR1 is the old name for PCB REV02 and REV01.
  • Power enable for PWR_GT and PWR_PS
EN_V_1V8_RFout16NONE3.3V_CPLD
  • EN_RF_ADC is the old name for PCB REV02 and REV01.
  • Power enable for PWR_ADC
EN_V_0V925_RFout24NONE3.3V_CPLD
  • EN_RF_DAC is the old name for PCB REV02 and REV01.
  • Power enable for PWR_DAC
RESETNin37NONE3.3V_CPLDReset pin (Active low)
PROG_Bout32NONE1.8V_CPLDFPGA reset PL configuration logic / currently_not_used
SRST_Bout33NONE1.8V_CPLDFPGA external system reset  / currently_not_used
POR_Bout4NONE1.8V_CPLDPower-On reset signal
MIO28_UART1_TXout29
1.8V_CPLDUART Transmission pin / currently_not_used
MIO28_UART1_RXin28
1.8V_CPLDUART Receive pin / currently_not_used
FPGA_IO0out27UP1.8V_CPLDFPGA GPIO  / User LED
FPGA_IO1inout26UP1.8V_CPLDFPGA GPIO / User dip switch interface
JTAG_TDOout48NONE3.3V_CPLDJTAG_B2B
JTAG_TDIin47UP3.3V_CPLDJTAG_B2B
JTAG_TCKin45NONE3.3V_CPLDJTAG_B2B
JTAG_TMSin44UP3.3V_CPLDJTAG_B2B
F_TDIout8NONE1.8V_CPLDJTAG ZynqMP
F_TMSout9NONE1.8V_CPLDJTAG ZynqMP
F_TCKout10NONE1.8V_CPLDJTAG ZynqMP
F_TDOin11NONE1.8V_CPLDJTAG ZynqMP
CPLD_JTAGENin41---3.3V_CPLDEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
INIT_Bin7---1.8V_CPLDFPGA PL initialization activity and configuration error signal / currently_not_used
DONEin12---1.8V_CPLDFPGA PL configuration done indicator
CPLD_IO0in43NONE3.3V_CPLDBOOT Mode input pin 0
CPLD_IO1in42NONE3.3V_CPLDBOOT Mode input pin 1
CPLD_IO2in40NONE3.3V_CPLDB2B to CPLD IO / Used as dip switch interface on the carrier board (After successful configuration of  FPGA is connected automatically with FPGA_IO1)
CPLD_IO3out38NONE3.3V_CPLDCPLD IO to B2B/ Used as power good, can be used to enable carrier periphery power


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.

CPLD_JTAGEN (B2B J1-30)S1-4 on TEB0835 Carrier BoardDescription
0OFFFPGA access
1ONCPLD access

Power

In this module the CPLD is responsible for controlling the power of the module. There are different power regulators or DC/DC converters whose outputs can be controlled by an enable signal. At the same time the outputs can also be monitored by power-good signals.


Power-on Sequencing

According to the AMD instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram for old and new PCB revisions.



PCB REV02, REV01
StageRelated Enable SignalVoltage DomainsRelated Power Good Signal
IDLE---------
STAGE1EN_PS_PL enabled (High)0.853V, 0.85V, 0.9VPG_PS_PL
STAGE2EN_GR1  enabled (High)1.8V, 0.85V, 1.2VPG_GR1
STAGE3EN_GR2 enabled (High)3.3V, 1.8VPG_GR2
STAGE4EN_VCCRF enabled (High)0.8534V, 1.158V, 3.3VPG_VCCRF
STAGE5

EN_RF_ADC enabled (High)

EN_RF_DAC enabled (High)

0.925V, 1.8V

0.925V, 1.8V, 2.5V 

PG_RF_ADC

PG_RF_DAC

WAIT_RDY---------
RDY

por enabled (High)

en1 enabled (High) if DONE is High.

---pg_all
  • pg_all <= PG_PS_PL & PG_GR1 & PG_GR2 & PG_VCCRF & PG_RF_ADC & PG_RF_DAC
  • If por is high then POR_B (power-on reset signal) will be deactivated.


PCB REV03
StageRelated Enable SignalVoltage DomainsRelated Power Good Signal
IDLE---------
STAGE 1EN_0V85 enabled (High)V_0V85

PG_0V85

STAGE 2EN_V_1V2  enabled (High)V_1V2

PG_V_1V2

STAGE 3EN_V_1V8_IO enabled (High)V_1V8_IOPG_V_1V8_IO
STAGE 4EN_V_3V3_IO enabled (High)V_3V3_IOPG_V_3V3_IO

EN_V_1V8_RF enabled (High)

V_1V8_DAC

PG_V_1V8_RF

STAGE 5

EN_V_0V925_RF

V_0V925_RF

PG_V_0V925_RF

WAIT_RDY---------
RDY

por enabled (High)

en1 will be enabled (High) if DONE is High.

---pg_all
  • pg_all →  (PG_V_1V2) and (PG_V_1V8_IO) and (PG_V_1V8_RF) and (PG_V_3V3_IO) and (PG_V_0V925_RF) and (PG_0V85)
  • If por is high then POR_B (power-on reset signal) will be deactivated.


Boot Mode

Boot Modes can be selected via B2B Pin Mode.

B2B Pin J1-28 (CPLD IO1)B2B Pin J1-26 (CPLD IO0)Boot Mode
00Boot from PS JTAG
01Boot from QSPI
11Boot from SD Card

I2C to GPIO

CPLD firmware consists of a I2C to GPIO block. This subsystem provides I2C protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via I2C bus interface protocol. The address of this block in the firmware is 0x20. In this case related I2C bus is bus 2 but the bus may be different depending on the vivado and linux design. These registers can be accessed with I2C commands in linux console or with i2c functions in FSBL code. To access these registers the following commands in linux console can be used:

  • To see the I2C bus addresses :                                     i2cdetect -y -r 2    
  • To read register of I2C to GPIO module:                            i2cget -y 2 0x20 <register address>     
  • To write data in a register of I2C to GPIO module:                 i2cset -y 2 0x20 <register address> <data>

 Access to the CPLD registers
RegisterAccess TypeDirectionAddressRelated command in linux consoleRelated command in FSBL
GPIO_input[7:0]ROutput data (reading from CPLD)0x00
i2cget -y 2 0x20 0x00
iic_read8(0x20,0x00,&data)
GPIO_input[15:8]ROutput data (reading from CPLD)0x01
i2cget -y 2 0x20 0x01
iic_read8(0x20,0x01,&data)
GPIO_input[23:16]ROutput data (reading from CPLD)0x02
i2cget -y 2 0x20 0x02
iic_read8(0x20,0x02,&data)
GPIO_input[31:24]ROutput data (reading from CPLD)0x03
i2cget -y 2 0x20 0x03
iic_read8(0x20,0x03,&data)


RegisterAccess TypeDirectionAddressRelated command in linux consoleRelated command in FSBL
GPIO_output[7:0]WInput data (writing to CPLD)0x00
i2cset -y 2 0x20 0x00 <data>
iic_write8(0x20,0x00,data)
GPIO_output[15:8]WInput data (writing to CPLD)0x01
i2cset -y 2 0x20 0x01 <data>
iic_write8(0x20,0x01,data)
GPIO_output[23:16]WInput data (writing to CPLD)0x02
i2cset -y 2 0x20 0x02 <data>
iic_write8(0x20,0x02,data)
GPIO_output[31:24]WInput data (writing to CPLD)0x03
i2cset -y 2 0x20 0x03 <data>
iic_write8(0x20,0x03,data)


RegisterUsed asDescription
GPIO_input[7:0]*CPLD_REVISION_MAJORFor exampel the value of the register for CPLD firmware revision REV02 is 0x02.
GPIO_input[15:8]*Boot mode

0x00 → Undefined

0x01 →  JTAG MODE

0x02 →  QSPI MODE

0x03 →  SD MODE

*The CPLD firmware revision and the boot mode are read out via the FSBL code during booting and output as information for the user in the Linux console during booting.


BitUsed asDescription
GPIO_output[24]Control bit for user LED (Green D1)

As default after booting is '1' (LED on) , if S1-C dip switch is set to OFF.

To set the LED off → Set the S1-C dip switch to ON or execute the following command in the linux console:

  •  i2cset -y 2 0x20 0x03 0x00


LED


StateBlink SequenceDescription
IDLEOFFPower Sequencing can not start. RESETN is active.
Stage 1*ooooooo
  • The faulty voltage can be:
    • V_0V85
  • The correct voltage is not present in the following nets:
    • RFSoC:
      • VCCINT, VCCINT_IO, VCCINT_AMS, VCCBRAM, VCC_PSINTTFP, VCC_PSINTTLP, VCC_PSINTFP_DDR, PS_MGTRAVCC, VCCSDFEC
Stage 2**oooooo
  • The faulty voltage can be:
    • V_1V2
    • MGTAVCC
  • The correct voltage is not present in the following nets:
    • RFSoC:
      • VCCO_PSDDR_504, MGTAVTT
    • DDR4-RAM1...4
      • VDD
      • VDDQ
Stage 3***ooooo
  • The faulty voltage can be:
    • 1.8V
  • The correct voltage is not present in the following nets:
    • RFSOC:
      • PS_MGTRAVTT, VCCAUX, VCCAUX_IO, VCC_PSAUX, VCCO_65, VCCO_PSIO_(500-503), EMMC(VCCQ)
    • ETH PL (DVDDH)
    • USB PHY (VDDIO)
    • QSPI

Stage 4

****oooo
  • The faulty voltage can be:
    • DAC_AVCCAUX
    • ADC_AVCCAUX
    • DDR_2V5
    • 3.3V
  • The correct voltage is not present in the following nets:
    • RFSoC:
      • VCCO_88
      • V_1V8_ADC_AVCCAUX
      • V_1V8_DAC_AVCCAUX
    • DDR_VTT LDO VDD
Stage 5*****ooo
  • The faulty voltage can be:
    • ADC_AVCC
    • DAC_AVCC
    • DAC_AVTT
  • The correct voltage is not present in the following nets:
    • RFSoC:
      • V_0V925_ADC_AVCC
      • V_0V925_DAC_AVCC
WAIT_RDY / RDY and DONE='0'******ooPower is ok. But the FPGA is not yet configured.
USR (RDY and DONE='1')*
  • ON after booting
  • User defined
Power is ok and the FPGA is configured successfully. LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high)
  • The period for every blink (*) is 0.5sec.
  • The (*) indicates that the LED is lit.
  • *  In this case FPGA is configured correctly and the LED is ON as default after booting, if the S1-C dip switch is set to OFF. The user can now control the LED through CPLD_IO2 either (Dip Switch S1-C) or I2C interface.

Appx. A: Change History and Legal Notices

Revision Changes

  • REV01 to REV02
    • The name of ports matched according to the schematic REV03.

    • The frequency of internal oscillator increased to 24.18MHz.

    • The power sequencing state machine changed.

    • I2C Subsystem added.

      • Address 0x20

      • FPGA_IO0 --> SCL

      • FPGA_IO1 --> SDA 

    • Generic parameter "VERSION" changed to "PCB_REVISION".

    • Two LED flashing states have been added.

    • The LED function changed.

    • The MIO28_UART1_TX and MIO28_UART1_RX ports added but these ports are not used in the code.
    • The POR_OVERRIDE_N port added. For PCB REV01 and REV02 is set to high impedance and for PCB REV03 is set to high. 
    • CPLD_IO2 (Dip switch S1-C) used for controlling the user LED (Green D1) after booting.
  • REV00 to REV01
    • Transfer Verilog to VHDL
    • power stage machine, add power down cycles on error state
    • Bugfix: Power Good (CPLD_IO3) depends now on module power sequencing
    • The LED status changed
    • The LED controllable by user after power-on.
    • The CPLD_IO2 signal connected to FPGA IO. (can be controlled by user)
    • The constrain file and buffer changed for JTAG.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV02REV03, REV02
  • The description of CPLD_IO2 signal in the document's port description table has been corrected.

2026-04-14

v.44

REV02REV03, REV02

Mohsen Chamanbaz

  • Corrections to the documentation for the LED status table

2025-02-03

v.41

REV02REV03, REV02

Mohsen Chamanbaz

  • REV02 release
    (SC-PGM-TE0835-02_03_SC0835-2P0_default_20250130.zip)

2020-11-02

v.29

REV01REV02, REV01

Mohsen Chamanbaz

  • REV01 release (firmware release 2020-10-27)
2020-08-18v.4REV00REV01 Ivan Girshchenko / Mohsen Chamanbaz
  • REV00 release (firmware release 2019-12-18)

All


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