Firmware for RFSoC module CPLD with designator U31: LCMX02-640HC
See Document Change History
| Name / opt. VHD Name | Direction | Pin | Pullup/Pulldown | Bank Power | Description |
|---|---|---|---|---|---|
| PWR_STATUS | out | 36 | NONE | 1.8V_CPLD | Output for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0) |
| MODE0 | out | 35 | NONE | 1.8V_CPLD | ZynqMP boot mode pin 0 |
| MODE1 | out | 3 | NONE | 1.8V_CPLD | ZynqMP boot mode pin 1 |
| MODE2 | out | 2 | NONE | 1.8V_CPLD | ZynqMP boot mode pin 2 |
| MODE3 | out | 5 | NONE | 1.8V_CPLD | ZynqMP boot mode pin 3 |
| PG_V_1V8_RF | in | 34 | NONE | 1.8V_CPLD |
|
| PG_V_1V8_IO | in | 31 | NONE | 1.8V_CPLD |
|
| PG_0V85 | in | 20 | NONE | 3.3V_CPLD |
|
| PG_V_1V2 | in | 21 | NONE | 3.3V_CPLD |
|
| PG_V_3V3_IO | in | 23 | NONE | 3.3V_CPLD |
|
| PG_V_0V925_RF | in | 17 | NONE | 3.3V_CPLD |
|
| EN_V_3V3_IO | out | 18 | NONE | 3.3V_CPLD |
|
| EN_V_1V8_IO | out | 19 | NONE | 3.3V_CPLD |
|
| EN_0V85 | out | 14 | NONE | 3.3V_CPLD |
|
| EN_V_1V2 | out | 15 | NONE | 3.3V_CPLD |
|
| EN_V_1V8_RF | out | 16 | NONE | 3.3V_CPLD |
|
| EN_V_0V925_RF | out | 24 | NONE | 3.3V_CPLD |
|
| RESETN | in | 37 | NONE | 3.3V_CPLD | Reset pin (Active low) |
| PROG_B | out | 32 | NONE | 1.8V_CPLD | FPGA reset PL configuration logic / currently_not_used |
| SRST_B | out | 33 | NONE | 1.8V_CPLD | FPGA external system reset / currently_not_used |
| POR_B | out | 4 | NONE | 1.8V_CPLD | Power-On reset signal |
| MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmission pin / currently_not_used | |
| MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin / currently_not_used | |
| FPGA_IO0 | out | 27 | UP | 1.8V_CPLD | FPGA GPIO / User LED |
| FPGA_IO1 | inout | 26 | UP | 1.8V_CPLD | FPGA GPIO / User dip switch interface |
| JTAG_TDO | out | 48 | NONE | 3.3V_CPLD | JTAG_B2B |
| JTAG_TDI | in | 47 | UP | 3.3V_CPLD | JTAG_B2B |
| JTAG_TCK | in | 45 | NONE | 3.3V_CPLD | JTAG_B2B |
| JTAG_TMS | in | 44 | UP | 3.3V_CPLD | JTAG_B2B |
| F_TDI | out | 8 | NONE | 1.8V_CPLD | JTAG ZynqMP |
| F_TMS | out | 9 | NONE | 1.8V_CPLD | JTAG ZynqMP |
| F_TCK | out | 10 | NONE | 1.8V_CPLD | JTAG ZynqMP |
| F_TDO | in | 11 | NONE | 1.8V_CPLD | JTAG ZynqMP |
| CPLD_JTAGEN | in | 41 | --- | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| INIT_B | in | 7 | --- | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal / currently_not_used |
| DONE | in | 12 | --- | 1.8V_CPLD | FPGA PL configuration done indicator |
| CPLD_IO0 | in | 43 | NONE | 3.3V_CPLD | BOOT Mode input pin 0 |
| CPLD_IO1 | in | 42 | NONE | 3.3V_CPLD | BOOT Mode input pin 1 |
| CPLD_IO2 | in | 40 | NONE | 3.3V_CPLD | B2B to CPLD IO / Used as dip switch interface on the carrier board (After successful configuration of FPGA is connected automatically with FPGA_IO1) |
| CPLD_IO3 | out | 38 | NONE | 3.3V_CPLD | CPLD IO to B2B/ Used as power good, can be used to enable carrier periphery power |
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN (B2B J1-30) | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
In this module the CPLD is responsible for controlling the power of the module. There are different power regulators or DC/DC converters whose outputs can be controlled by an enable signal. At the same time the outputs can also be monitored by power-good signals.
According to the AMD instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram for old and new PCB revisions.
| PCB REV02, REV01 | |||
|---|---|---|---|
| Stage | Related Enable Signal | Voltage Domains | Related Power Good Signal |
| IDLE | --- | --- | --- |
| STAGE1 | EN_PS_PL enabled (High) | 0.853V, 0.85V, 0.9V | PG_PS_PL |
| STAGE2 | EN_GR1 enabled (High) | 1.8V, 0.85V, 1.2V | PG_GR1 |
| STAGE3 | EN_GR2 enabled (High) | 3.3V, 1.8V | PG_GR2 |
| STAGE4 | EN_VCCRF enabled (High) | 0.8534V, 1.158V, 3.3V | PG_VCCRF |
| STAGE5 | EN_RF_ADC enabled (High) EN_RF_DAC enabled (High) | 0.925V, 1.8V 0.925V, 1.8V, 2.5V | PG_RF_ADC PG_RF_DAC |
| WAIT_RDY | --- | --- | --- |
| RDY | por enabled (High) en1 enabled (High) if DONE is High. | --- | pg_all |
| PCB REV03 | |||
|---|---|---|---|
| Stage | Related Enable Signal | Voltage Domains | Related Power Good Signal |
| IDLE | --- | --- | --- |
| STAGE 1 | EN_0V85 enabled (High) | V_0V85 | PG_0V85 |
| STAGE 2 | EN_V_1V2 enabled (High) | V_1V2 | PG_V_1V2 |
| STAGE 3 | EN_V_1V8_IO enabled (High) | V_1V8_IO | PG_V_1V8_IO |
| STAGE 4 | EN_V_3V3_IO enabled (High) | V_3V3_IO | PG_V_3V3_IO |
EN_V_1V8_RF enabled (High) | V_1V8_DAC | PG_V_1V8_RF | |
| STAGE 5 | EN_V_0V925_RF | V_0V925_RF | PG_V_0V925_RF |
| WAIT_RDY | --- | --- | --- |
| RDY | por enabled (High) en1 will be enabled (High) if DONE is High. | --- | pg_all |
Boot Modes can be selected via B2B Pin Mode.
| B2B Pin J1-28 (CPLD IO1) | B2B Pin J1-26 (CPLD IO0) | Boot Mode |
|---|---|---|
| 0 | 0 | Boot from PS JTAG |
| 0 | 1 | Boot from QSPI |
| 1 | 1 | Boot from SD Card |
CPLD firmware consists of a I2C to GPIO block. This subsystem provides I2C protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via I2C bus interface protocol. The address of this block in the firmware is 0x20. In this case related I2C bus is bus 2 but the bus may be different depending on the vivado and linux design. These registers can be accessed with I2C commands in linux console or with i2c functions in FSBL code. To access these registers the following commands in linux console can be used:
To see the I2C bus addresses : i2cdetect -y -r 2
To read register of I2C to GPIO module: i2cget -y 2 0x20 <register address>
To write data in a register of I2C to GPIO module: i2cset -y 2 0x20 <register address> <data>
| Register | Access Type | Direction | Address | Related command in linux console | Related command in FSBL |
|---|---|---|---|---|---|
| GPIO_input[7:0] | R | Output data (reading from CPLD) | 0x00 | i2cget -y 2 0x20 0x00 | iic_read8(0x20,0x00,&data) |
| GPIO_input[15:8] | R | Output data (reading from CPLD) | 0x01 | i2cget -y 2 0x20 0x01 | iic_read8(0x20,0x01,&data) |
| GPIO_input[23:16] | R | Output data (reading from CPLD) | 0x02 | i2cget -y 2 0x20 0x02 | iic_read8(0x20,0x02,&data) |
| GPIO_input[31:24] | R | Output data (reading from CPLD) | 0x03 | i2cget -y 2 0x20 0x03 | iic_read8(0x20,0x03,&data) |
| Register | Access Type | Direction | Address | Related command in linux console | Related command in FSBL |
|---|---|---|---|---|---|
| GPIO_output[7:0] | W | Input data (writing to CPLD) | 0x00 | i2cset -y 2 0x20 0x00 <data> | iic_write8(0x20,0x00,data) |
| GPIO_output[15:8] | W | Input data (writing to CPLD) | 0x01 | i2cset -y 2 0x20 0x01 <data> | iic_write8(0x20,0x01,data) |
| GPIO_output[23:16] | W | Input data (writing to CPLD) | 0x02 | i2cset -y 2 0x20 0x02 <data> | iic_write8(0x20,0x02,data) |
| GPIO_output[31:24] | W | Input data (writing to CPLD) | 0x03 | i2cset -y 2 0x20 0x03 <data> | iic_write8(0x20,0x03,data) |
| Register | Used as | Description |
|---|---|---|
| GPIO_input[7:0]* | CPLD_REVISION_MAJOR | For exampel the value of the register for CPLD firmware revision REV02 is 0x02. |
| GPIO_input[15:8]* | Boot mode | 0x00 → Undefined 0x01 → JTAG MODE 0x02 → QSPI MODE 0x03 → SD MODE |
*The CPLD firmware revision and the boot mode are read out via the FSBL code during booting and output as information for the user in the Linux console during booting.
| Bit | Used as | Description |
|---|---|---|
| GPIO_output[24] | Control bit for user LED (Green D1) | As default after booting is '1' (LED on) , if S1-C dip switch is set to OFF. To set the LED off → Set the S1-C dip switch to ON or execute the following command in the linux console:
|
| State | Blink Sequence | Description |
|---|---|---|
| IDLE | OFF | Power Sequencing can not start. RESETN is active. |
| Stage 1 | *ooooooo |
|
| Stage 2 | **oooooo |
|
| Stage 3 | ***ooooo |
|
Stage 4 | ****oooo |
|
| Stage 5 | *****ooo |
|
| WAIT_RDY / RDY and DONE='0' | ******oo | Power is ok. But the FPGA is not yet configured. |
| USR (RDY and DONE='1')* |
| Power is ok and the FPGA is configured successfully. LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high) |
The name of ports matched according to the schematic REV03.
The frequency of internal oscillator increased to 24.18MHz.
The power sequencing state machine changed.
I2C Subsystem added.
Address 0x20
FPGA_IO0 --> SCL
FPGA_IO1 --> SDA
Generic parameter "VERSION" changed to "PCB_REVISION".
Two LED flashing states have been added.
The LED function changed.
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| REV02 | REV03, REV02 |
| |||
2026-04-14 | v.44 | REV02 | REV03, REV02 | Mohsen Chamanbaz |
|
2025-02-03 | v.41 | REV02 | REV03, REV02 | Mohsen Chamanbaz |
|
2020-11-02 | v.29 | REV01 | REV02, REV01 | Mohsen Chamanbaz |
|
| 2020-08-18 | v.4 | REV00 | REV01 | Ivan Girshchenko / Mohsen Chamanbaz |
|
| All |
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