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Table of contents

Table of Contents
outlinetrue

Overview

Firmware for PCB RFSoC module CPLD with designator U31. Second CPLD Device in Chain: LCMX02-640HC

Feature Summary

  • Firmware
  • Power Management
  • JTAG routing
  • LED

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Name / opt. VHD NameDirectionPinBank PowerDescription
MIO13PWR_STATUSout361.8V_CPLDOutput to drive gate of MOSFET transistor for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0)
MODE0out351.8V_CPLDZynqMP boot mode pin 0
PG_VCCRFin341.8V_CPLDPower Good input from PWR_PRE
SRST_Bout331.8V_CPLDFPGA external system reset  / currently_not_used
PROG_Bout321.8V_CPLDFPGA reset PL configuration logic / currently_not_used
PG_GR2in311.8V_CPLDPower control input from PWR_PS and PWR_DDR
MIO28_UART1_TXout291.8V_CPLDUART Transmition pin / currently_not_used
MIO28_UART1_RXin281.8V_CPLDUART Receive pin / currently_not_used
FPGA_IO0inoutout271.8V_CPLDFPGA GPIO / currently_not_usedGPIO  / User LED
FPGA_IO1inoutin261.8V_CPLDFPGA GPIO / currently_not_usedUser dip switch interface
EN_PS_PLout143.3V_CPLDPower enable for PWR_CORE , PWR_PS and PWR_GT
EN_GR1out153.3V_CPLDPower enable for PWR_GT and PWR_PS
EN_RF_ADCout163.3V_CPLDPower enable for PWR_ADC
PG_RF_DACin173.3V_CPLDPower control input from PWR_DAC
EN_VCCRFout183.3V_CPLDPower enable for PWR_PRE
EN_GR2out193.3V_CPLDPower enable for PWR_DDR , PWR_GT and PWR_PS
PG_PS_PLin203.3V_CPLDpower control input from PWR_CORE , PWR_GT and PWR_PS
PG_GR1in213.3V_CPLDPower control input from PWR_GT and PWR_PS
PG_RF_ADCin233.3V_CPLDPower control input from PWR_ADC
EN_RF_DACout243.3V_CPLDPower enable for PWR_DAC
MODE2out21.8V_CPLDZynqMP boot mode pin 2
MODE1out31.8V_CPLDZynqMP boot mode pin 1
POR_Bout41.8V_CPLDPower-On reset signal
MODE3out51.8V_CPLDZynqMP boot mode pin 3
INIT_Bin71.8V_CPLDFPGA PL initialization activity and configuration error signal / currently_not_used
F_TDIout81.8V_CPLDJTAG ZynqMP
F_TMSout91.8V_CPLDJTAG ZynqMP
F_TCKout101.8V_CPLDJTAG ZynqMP
F_TDOin111.8V_CPLDJTAG ZynqMP
DONEin121.8V_CPLDFPGA PL configuration done indicator / currently_not_used
JTAG_TDOout483.3V_CPLDJTAG_B2B
JTAG_TDIin473.3V_CPLDJTAG_B2B
JTAG_TCKin453.3V_CPLDJTAG_B2B
JTAG_TMSin443.3V_CPLDJTAG_B2B
CPLD_IO0in433.3V_CPLDBOOT Mode input pin 0
CPLD_IO1in423.3V_CPLDBOOT Mode input pin 1
CPLD_JTAGENin413.3V_CPLDEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
CPLD_IO2inout403.3V_CPLDCPLD IO / currently_not_usedto B2B / Used as dip switch interface on the carrier board (After successful configuration of  FPGA is connected automatically with FPGA_IO1)
CPLD_IO3inout383.3V_CPLDCPLD IO / currently_not_usedto B2B/ Used as power good, can be used to enable carrier periphery power
RESETNin373.3V_CPLDReset pin of CPLD (Active low)


Firmware

See Document Change History.

Functional Description

JTAG

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According to the Xilinx instructions the power regulator or DC-DC converter must be switched on or off in a certain order. This is called power-on or power-off sequencing.To implement power-on sequencing correctly, a state machine must be running there. In the following you can see the State Machine Diagram.

Image Removed

LED


draw.io Diagram
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diagramNameState Machine Diagram 2
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width1200
linksauto
tbstyletop
diagramDisplayName
lboxtrue
diagramWidth1284
revision29


StageControlVoltage DomainsSignal Monitoring to change stage
IDLE---------
STAGE0EN_PS_PL enabled (High)0.853V, 0.85V, 0.9V---
STAGE1EN_GR1  enabled (High)1.8V, 0.85V, 1.2VPG_PS_PL
STAGE2EN_GR2 enabled (High)3.3V, 1.8VPG_GR1
STAGE3EN_VCCRF enabled (High)0.8534V, 1.158V, 3.3VPG_GR2
STAGE4

EN_RF_ADC enabled (High)

EN_RF_DAC enabled (High)

0.925V, 1.8V

0.925V, 1.8V, 2.5V 

PG_VCCRF
STAGE5------

PG_RF_ADC

PG_RF_DAC

WAIT_RDY------pg_all
RDYpor enabled (High)---pg_all
  • pg_all <= PG_PS_PL & PG_GR1 & PG_GR2 & PG_VCCRF & PG_RF_ADC & PG_RF_DAC
  • If por is high then POR_B (power-on reset signal) will be deactivated.


LED

1**********oOne of Power is ok
StatesPower StageBlink SequenceComment
IDLE***************oooooooooooooooooooo*Power Sequencing can not start. RESETN is active.
Stage 0ooooooooooooooooo*o*First enable signal (EN_PS_PL) is activated.
Stage 1ooooooooooooooo*o*o*The correct voltage in one ***********o*oOne of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC
Stage 2ooooooooooooo*o*o*o*The correct voltage in one of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT
Stage 23ooooooooooo*o********o*o*o*oThe correct voltage in one of One of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2
Stage 34ooooooooo*o******o*o*o*o*oThe correct voltage in one of One of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3
Stage 45ooooooo***o**o*o*o*o*o*oThe correct voltage in one of One of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT
WAIT_RDYooooo*o*o*o*o*o*o*o*All power good signals are checked again.
RDYOFFPower is ok.
ERRORo*o*o*o*o*o*o*o*oOne of the last stages is not okRDYoooooooooooooooo*o*The main power supply must be switched off.
USRUser definedLED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high)
  • The period for erery blink (*o) is 0.5sec.

Boot Mode

Boot Modes can be selected via B2B Pin Mode.

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Appx. A: Change History and Legal Notices

Revision Changes

  • REV00 REV01 to REV01REV02

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.

REV01REV02, REV01

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modified-user
modified-user

  • working in processREV02 release
2020-08-18v.4REV00REV01 Ivan Girshchenko / Mohsen Chamanbaz
  • REV01 release (firmware release 2019-12-18)

All

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modified-users


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