Page History
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| draw.io Diagram | ||||||||||||||||||||||
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| Stage | Control | Voltage Domains | Signal Monitoring to change stage |
|---|---|---|---|
| IDLE | --- | --- | --- |
| STAGE0 | EN_PS_PL enabled (High) | 0.853V, 0.85V, 0.9V | --- |
| STAGE1 | EN_GR1 enabled (High) | 1.8V, 0.85V, 1.2V | PG_PS_PL |
| STAGE2 | EN_GR2 enabled (High) | 3.3V, 1.8V | PG_GR1 |
| STAGE3 | EN_VCCRF enabled (High) | 0.8534V, 1.158V, 3.3V | PG_GR2 |
| STAGE4 | EN_RF_ADC enabled (High) EN_RF_DAC enabled (High) | 0.925V, 1.8V 0.925V, 1.8V, 2.5V | PG_VCCRF |
| STAGE5 | --- | --- | PG_RF_ADC PG_RF_DAC |
| WAIT_RDY | --- | --- | pg_all |
| RDY | por enabled (High) | --- | pg_all |
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Appx. A: Change History and Legal Notices
Revision Changes
- REV00 to REV01 to REV02
- transfer verilog to vhdl
- power stagemachine, add power down cyclus on error state
- bugfix: PGGood(CPLD_IO3) depends now on modul power sequencing
- LED status changed
- LED controllable by USR after power up
- CPLD_IO2 connected to FPGA IO (can be controlled by user)
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV01 | REV02, REV01 |
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| 2020-08-18 | v.4 | REV00 | REV01 | Ivan Girshchenko / Mohsen Chamanbaz |
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| All |
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