Page History
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
Power
In this module the CPLD is responsible for controlling the power of the module. There are different power regulators or DC/DC converters whose outputs can be controlled by an enable signal. At the same time the outputs can also be monitored by power-good signals.
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| Stage | Control | Voltage Domains | Signal Monitoring to change stage |
|---|---|---|---|
| IDLE | --- | --- | --- |
| STAGE0 | EN_PS_PL enabled (High) | 0.853V, 0.85V, 0.9V | --- |
| STAGE1 | EN_GR1 enabled (High) | 1.8V, 0.85V, 1.2V | PG_PS_PL |
| STAGE2 | EN_GR2 enabled (High) | 3.3V, 1.8V | PG_GR1 |
| STAGE3 | EN_VCCRF enabled (High) | 0.8534V, 1.158V, 3.3V | PG_GR2 |
| STAGE4 | EN_RF_ADC enabled (High) EN_RF_DAC enabled (High) | 0.925V, 1.8V 0.925V, 1.8V, 2.5V | PG_VCCRF |
| STAGE5 | --- | --- | PG_RF_ADC PG_RF_DAC |
| WAIT_RDY | --- | --- | pg_all--- |
| RDY | por enabled (High) | --- | pg_all |
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- REV00 to REV01
- transfer verilog to vhdl
- power stagemachine, add power down cyclus on error state
- bugfix: PGGoodPower Good(CPLD_IO3) depends now on modul module power sequencing
- LED status changed
- LED controllable by USR after power up
- CPLD_IO2 connected to FPGA IO (can be controlled by user)
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Overview
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