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| States | Blink Sequence | Comment | |||
|---|---|---|---|---|---|
| IDLE | ooooooooooooooooooo* | Power Sequencing can not start. RESETN is active. | |||
| Stage 0 | ooooooooooooooooo*o* | First enable signal (EN_PS_PL) is activated. | |||
| Stage 1 | ooooooooooooooo*o*o* | The correct voltage in one of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC | |||
| Stage 2 | ooooooooooooo*o*o*o* | The correct voltage in one of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT | |||
| Stage 3 | ooooooooooo*o*o*o*o* | The correct voltage in one of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2 | |||
| Stage 4 | ooooooooo*o*o*o*o*o* | The correct voltage in one of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3 | |||
| Stage 5 | ooooooo*o*o*o*o*o*o* | The correct voltage in one of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT | |||
| WAIT_RDY / RDY | ooooo*o*o*o*o*o*o*o* | All power good signals are checked again. | RDY | OFF | / Power is ok. |
| ERROR | o*o*o*o*o*o*o*o*o*o* | The main power supply must be switched off. | |||
| USR | User defined | LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high) |
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