Page History
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| Info |
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2 Firmware variants with swapped external reset input and output direction are available. See Watchdog 105689936 section of this document. Firmware (SC729_03_default_teb0729_02_plus.jed) for J2-89 as external reset output and J2-91 as external reset input will be used as default firmware. |
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| Warning |
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Watchdog do not work correctly on all modules with Firmware released before 2017.08.22. Please update Firmware on CPLD. For questions, write to Trenz Electronic support. |
Feature Summary
- Boot Mode
- JTAG connection
- Power Management
- Watchdog Management
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| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| BOARD_STAT | out | 23 | STATUS to B2B |
| BOOT_MODE1 | in | 28 | Boot Mode Pin from B2B |
| BOOT_MODE2 | in | 27 | Boot Mode Pin from B2B |
| BOOT1 | out | 13 | Boot Mode Pin to FPGA (MIO4) |
| BOOT2 | out | 12 | Boot Mode Pin to FPGA (MIO5) |
| EN_3V3 | out | 25 | Enable 3.3V Switch |
| F_TCK | out | 8 | JTAG to FPGA |
| F_TDI | out | 9 | JTAG to FPGA |
| F_TDO | in | 11 | JTAG from FPGA |
| F_TMS | out | 10 | JTAG to FPGA |
| FPGA_IO | in | 5 | USR Status output from FPGA |
| JTAGSEL | --- | 26 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to FPGA, one: CPLD access) |
| nRST | inout | 16 | External Reset. Direction Firmware depends, see Watchdog section |
| nRST_IN | inout | 4 | External Reset. Direction Firmware depends, see Watchdog section |
| PS_POR_B | in | 14 | Reset from Watchdog to FPGA |
| TCK | in | 30 | JTAG from B2B |
| TDI | in | 32 | JTAG from B2B |
| TDO | out | 1 | JTAG to B2B |
| TMS | in | 29 | JTAG from B2B |
| WD_EN | in | 21 | Watchdog PL I/O |
| WD_HIT | in | 20 | Watchdog PL I/O |
| WDI | out | 17 | Watchdog trigger to external Watchdog IC |
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Functional Description
JTAG
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Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.
| Pin | FPGA IO |
|---|---|
| BOOT_MODE1 (BOOT1) | MIO4 |
| BOOT_MODE2 (BOOT2) | MIO5 |
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TPS3310K33DMVR WDI Timing Requirenments:
| Time-out period | tT(OUT) | at WDI | min 0,55s, typ 1,1s, max 1,65s |
| Pulse width | tw | at WDI | 300ns |
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 Figure1: Firmware (SC729_03_teb0729_02_org.jed) for TEB0729 without HW modification,
|  Figure2: Firmware (SC729_03_default_teb0729_02_plus.jed) for TEB0729 with HW modification,
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B2B Control:
2 Variant available,depends on carrier board connection, see Figure 1 and 2. The swapped signals and nRST_IN pulse limitation on variant 1 are the only difference between this two variants.
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WD_HIT pulse will be forwarded to WDI pin, if WE_EN is high and min 16 WD_HIT from FPGA was detected. To disable FPGA Control, set WD_EN to lowcan't be disabled until module was reboot.
WDI max. pulse width: tw(FPGA)<tT(out)- tw(CPLD)
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Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV03 to REV04
- Remove possibility to disable WD again via FPGA
CPLD REV02 to REV03
- Add power up Watchdog main reset from CPLD
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV03REV04 | REV02/REV02plus/REV03 |
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| 2017-10-25 | v.17 | REV03 | REV02/REV02plus/REV03 | John Hartfiel |
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| 2017-08-31 | v.14 | REV02 | REV02/REV02plus | John Hartfiel | ||||||||||||||||||||||||||||
| 2017-08-23 | v.13 | REV02 | REV02/REV02plus | John Hartfiel |
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| 2017-06-07 | REV02 | REV02/REV02plus |
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| All |
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Legal Notices
| Include Page | ||||
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