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Firmware for PCB CPLD with designator U6. Second CPLD Device in Chain: LCMX02-256HC

2 Firmware variants with swapped external reset input and output direction are available. See Watchdog section of this document. Firmware (SC729_03_default_teb0729_02_plus.jed) for J2-89 as external reset output and J2-91 as external reset input will be used as default firmware.

Watchdog do not work correctly on all modules with Firmware released before 2017.08.22. Please update Firmware on CPLD. For questions, write to Trenz Electronic support.


Feature Summary

  • Boot Mode
  • JTAG connection
  • Power Management
  • Watchdog Management

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
BOOT_MODE1in28Boot Mode Pin from B2B
BOOT_MODE2in27Boot Mode Pin from B2B
BOOT1out13Boot Mode Pin to FPGA (MIO4)
BOOT2out12Boot Mode Pin to FPGA (MIO5)
EN_3V3out25Enable 3.3V Switch
FPGA_IOin5USR Status output from FPGA
JTAGSEL---26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to FPGA, one: CPLD access)
nRSTinout16External Reset. Direction Firmware depends, see Watchdog section
nRST_INinout4External Reset. Direction Firmware depends, see Watchdog section
PS_POR_Bin14Reset from Watchdog to FPGA
TCKin30JTAG from B2B
TDIin32JTAG from B2B
TDOout1JTAG to B2B
TMSin29JTAG from B2B
WD_ENin21Watchdog  PL I/O
WD_HITin20Watchdog  PL I/O
WDIout17Watchdog trigger to external Watchdog IC


Functional Description


JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGSEL (logical one for CPLD, logical zero for FPGA) on J2-111.


3.3V (EN_3V3) is enabled on power up.

Boot Mode

Boot Mode Pins routed through the CPLD. MIO2 and MIO3 are connected to GND via resistor.


10not supported


Watchdog (TPS3310K33DMVR) is controlled by B2B IO, CPLD, Zynq IO or 1V power supply voltage.

TPS3310K33DMVR WDI Timing Requirenments:

Time-out periodtT(OUT)at WDImin 0,55s, typ 1,1s, max 1,65s
Pulse widthtwat WDI300ns

Firmware Variants:

Figure1: Firmware (SC729_03_teb0729_02_org.jed) for TEB0729 without HW modification,

  • J2-89 external reset input
  • J2-91 external reset output

Figure2: Firmware (SC729_03_default_teb0729_02_plus.jed) for TEB0729 with HW modification,

  • J2-89 external reset output
  • J2-91 external reset input


B2B Control:

2 Variant available,depends on carrier board connection, see Figure 1 and 2. The swapped signals and  nRST_IN pulse limitation on variant 1 are the only difference between this two variants.

Variant 1 (Figure 1, SC729_rev02org.jed):

nRSTJ2-89inoutMain Reset to module
nRST_INJ2-91outMain reset to carrier and PS_POR_B for approx. 1,9 us.

Variant 2 (Figure 2, SC729_rev02plus.jed):

nRSTJ2-89outMain reset to carrier and PS_POR_B
nRST_INJ2-91inoutMain Reset to module

1V Power supply:

Reset PS, if 1V drop down. Connected on PCB, controlled by WD SENSE pin.

CPLD Control:

CPLD controlled WD on power up until FPGA takes control via WE_EN and WD_HIT input. CPLD WDI pulse frequency is set to approx. 1ms (Pulse width tw(CPLD)=507us )

nRST_IN is set to GND on power up for short time periode

FPGA Control:

WD_HIT pulse will be forwarded to WDI pin, if WE_EN is high and min 16 WD_HIT from FPGA was detected. To disable FPGA Control, set WD_EN to low.

WDI max. pulse width:  tw(FPGA)<tT(out)- tw(CPLD)

Status / GPIO

BOARD_STAT is used as WD restart indicator and as user IO.

Slow BlinkIf PS_POR_B is low and appr. 16s after PS_POR_B goes up
FPGA_IOUser defined, appr. 16s after PS_POR_B goes up and as long as PS_POR_B is high

Info: On TEB0729, signal is connected to XMOD LED.

Appx. A: Change History and Legal Notices

Revision Changes


  • Add power up Watchdog main reset from CPLD


  • Bugfix for TE0729-REV02 Watchdog support
  • Add 2 Variants for TEB0729-REV02 and TE0729-REV02_MOD support
  • Change Pin FGPA_IO direction
  • Change Pin BOARD_STAT output configuration

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription



  • REV03 finished
2017-08-31v.14REV02REV02/REV02plusJohn Hartfiel
REV02REV02/REV02plusJohn Hartfiel
  • REV02 finished
  • Initial release

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