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Template Revision 21.8 0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 TEI0006 Test Board"


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Notes :

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DateQuartusProject BuiltAuthorsDescription
2020-10-1919.4 Pro

TEI0006-test_board_noprebuilt-quartus_19.4.0-20201019101920.zip

TEI0006-test_board-quartus_19.4.0-20201019101840.zip

Thomas Dück
  • script update
  • bugfixes
2020-05-1319.4 Pro

TEI0006-test_board_noprebuilt-quartus_19.4.0-20200513124953.zip

TEI0006-test_board-quartus_19.4.0-20200513125247.zip

Thomas Dück
  • TE scripts update
2020-03-0919.4 Pro

TEI0006-test_board-quartus_19.4-20200309134933.zip
TEI0006-test_board_noprebuilt-quartus_19.4-20200309135555.zip

Thomas Dück
  • initial release


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Notes :

  • prebuilt files
  • Template Table:

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      titlePrebuilt files

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      BIN-

      File

      File-Extension

      Description

      BIF-SOPC Information File*.bifsopcinfoFile with description to generate Bin-Fileof the .qsys file to create software for the target hardware
      SRAM Object File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-sofRam configuration file
      Programmer Object File*.bitpofFPGA (PL Part) Configuration FileDebugProbes-Fileconfiguration file
      JTAG indirect configuration file*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      jicFlash configuration file
      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

      application for NIOS II processor system




Scroll Title
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File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
SRAM Object File*.sofRam configuration file
JTAG indirect configuration file*.jicFlash configuration file
Diverse Reports---Report files in different formats
Software-Application-File*.elfSoftware application for NIOS II processor system


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Reference Design is available on:

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  1. Prepare HW like described on section Programming 94490007
  2. Connect UART USB (most cases same as JTAG)
  3. Connect your board to the network
  4. Power on PCB

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Note:

  • Description of Block Design , Constrains- Project, Block Design - Platform Desginer, ... BD Block Design Pictures from Export...

Block Design

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titleBlock Design - Project
Block Design - test_board.bdf

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General Example:

hello_tei0006

Hello TEI0006 is a Quartus Hello World example as endless loop instead of one console output.

Template location: <design_name>/source_files/software/

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DateDocument Revision

Authors

Description

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  • script update
  • bugfixes
2020-05-13v.5Thomas Dück
  • Design files update
2020-03-18v.4Thomas Dück
  • initial release 19.4
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

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