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Template Revision 21.8 0 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 TEI0006 Test Board" |
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Date | Quartus | Project Built | Authors | Description |
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2020-0510-1319 | 19.4 Pro | TEI0006-test_board_noprebuilt-quartus_19.4.0-2020051312495320201019101920.zip TEI0006-test_board-quartus_19.4.0-2020051312524720201019101840.zip | Thomas Dück | - TE scripts script update
- bugfixes
| 2020- | 0305- | 0913 | 19.4 Pro | TEI0006-test_board_noprebuilt-quartus_19.4.0- | 2020030913493320200513124953.zip TEI0006-test_board | _noprebuilt-quartus_19.4.0- | 2020030913555520200513125247.zip | Thomas Dück | |
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Release Notes and Know Issues
| 2020-03-09 | 19.4 Pro | TEI0006-test_board-quartus_19.4-20200309134933.zip TEI0006-test_board_noprebuilt-quartus_19.4-20200309135555.zip | Thomas Dück | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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Notes : - prebuilt files
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File | File-Extension | Description |
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BIF-SOPC Information File | *.bifsopcinfo | File with description to generate Bin-Fileof the .qsys file to create software for the target hardware | SRAM Object BIN- File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | sof | Ram configuration file | Programmer Object BIT- File | *.bitpof | FPGA (PL Part) Configuration FileDebugProbes-Fileconfiguration file | JTAG indirect configuration file | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | jic | Flash configuration file | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | HardwareSoftware-PlatformApplication-Specification-FilesFile | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware |
SRAM Object File | *.sof | Ram configuration file |
JTAG indirect configuration file | *.jic | Flash configuration file |
Diverse Reports | --- | Report files in different formats |
Software-Application-File | *.elf | Software application for NIOS II processor system |
Download
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
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elf | Software application for NIOS II processor system |
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File | File-Extension | Description |
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SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware | SRAM Object File | *.sof | Ram configuration file | JTAG indirect configuration file | *.jic | Flash configuration file | Diverse Reports | --- | Report files in different formats | Software-Application-File | *.elf | Software application for NIOS II processor system |
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Download
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
- Open create_project_win.cmd/create_project_linux.sh:
Image Added'Create Project' GUI example - Select Board in "Board selection"
- Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<design_name>/settings/design_basic_settings.tcl"
Launch
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
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Note: - Programming and Startup procedure
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
QSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd
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- /create_project_linux.sh
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- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 94490007
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
- Open Serial Console (e.g. PuTTY)
- COM Port: Win OS see device manager, Linux OS see dmesg | grep tty (UART is *USB1)
- Speed: 11520
- Select "Implicit CR in every LF" in category "Terminal"
- Press reset button
- Simple Socket Server is starting up. Follow instructions on shell.
- If dhcp server is not available: open software project in sdk gui (e.g. NIOS II SBT for Eclipse) and change predefined IP address in "simple_socket_server.h", rebuild software project and download *.elf file to the device.
- Open command shell and enter "telnet <ip_address> 30" to connect to simple socket server
System Design - Quartus
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Block Design
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title | Block Design - Project |
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Image AddedBlock Design - test_board.bdf |
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Image AddedBlock Design - NIOS_test_board.qsys |
Software Design - SDK
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
- Open create_project_win.cmd/create_project_linux.sh:
Image Removed'Create Project' GUI example - Select Board in "Board selection"
- Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<design_name>/settings/design_basic_settings.tcl"
Launch
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
QSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd/create_project_linux.sh
- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
- Open Serial Console (e.g. PuTTY)
- COM Port: Win OS see device manager, Linux OS see dmesg | grep tty (UART is *USB1)
- Speed: 11520
- Select "Implicit CR in every LF" in category "Terminal"
- Press reset button
- Simple Socket Server is starting up. Follow instructions on shell.
- If dhcp server is not available: open software project in sdk gui (e.g. NIOS II SBT for Eclipse) and change predefined IP address in "simple_socket_server.h", rebuild software project and download *.elf file to the device.
- Open command shell and enter "telnet <ip_address> 30" to connect to simple socket server
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Block Design
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Image RemovedBlock Design - NIOS_test_board.qsys |
Software Design - SDK
Application
Application
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---------------------------------------------------------- General Example: hello_tei0006Hello TEI0006 is a Quartus Hello World example as endless loop instead of one console output. |
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id | Comments |
Template location: <design_name>/source_files/software/
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| | 2020-05-13 | v.5 | Thomas Dück | | 2020-03-18 | v.4 | Thomas Dück | | -- | all | Page info |
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