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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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B2B Connector | Interface | I/O Signal Count | Connected to | Notes |
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JB1
| Ethernet LAN | 8x Single ended, 4x Diff pairs | RJ45 Socket, J2 |
| SD Card | 6 x Single Ended | IO Expander, U4 |
| I/Os | 20x Single Ended | FPGA BAnk 6, U6 |
| CRUVI | 20x Single ended, 10x Diff pairs 4x Single Ended | High Speed CRUVI, J12 | CRUVI C | Control Signals | 5x Single Ended | FPGA, U6 |
| I/Os | 8x Single ended | FPGA Bank 8, U6 |
| VBAT | 1x Single Ended | Pin Header, J3 |
| JB2
| CRUVI | 8x Single ended, 4x Diff pairs 4x Single Ended | High Speed CRUVI, J10 | CRUVI A | CRUVI | 12x Single ended, 6x Diff pairs | High Speed CRUVI, J11 | CRUVI B | JTAG | 4x Single Ended | FPGA Bank 5, U6 |
| JB3 | CRUVI | 12x Single ended, 6x Diff pairs 4x Single Ended | High Speed CRUVI, J11 | CRUVI B | USB | 4x Single Ended | USB A, J9 |
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Scroll Title |
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anchor | Table_SIP_CRUVIB2B |
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title | CRUVI B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Speed | Designators | Schematic | Connected to | Notes |
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High |
J12 | VCCIO_CC | B2B, J11 | GPIO | CC_SMB | B2B, J11 | SC SPI | J11 | A_X6...7 | B2B, J11 | I2C0 SDA/SCL | B_X0...7| | B2B, J11 | GPIO |
| CRUVI C, J12 | A0...A5 (N/P) | B2B, JB1 |
| B0...B5 (N/P) | B2B, JB1 |
| MODE REFCLK | FPGA Bank 8, U6 |
| SMB_ALERT SMB_SDA SMB_SCL | FPGA Bank 8, U6 |
| DI,DO,SCK,SEL | FPGA Bank 8, U6 |
| HSIO, HI, HO | B2B, JB1 |
| RESET | B2B, JB1 |
| High
| CRUVI B, J11 | A0...A5 (N/P) | B2B, JB1 |
| B0...B5 (N/P) | B2B, JB1 |
| MODE REFCLK | FPGA Bank 3, U6 |
| SMB_ALERT SMB_SDA SMB_SCL | FPGA Bank 2, U6 |
| DI,DO,SCK,SEL | FPGA Bank 2, U6 |
| HSIO, HI, HO | B2B, JB3 |
| RESET | B2B, JB3 |
| High
| CRUVI A, |
J10 | C_X0...7 | B2B, J11 | GPIO | Low | J11 J11B2B, J11 | RESET | B2B, J11B2B J11B2B, J11 | SPI | FPGA Bank 2, U6 |
| HSIO, HI, HO | B2B, JB2 |
| RESET | B2B, JB2 |
| Low | CRUVI | X0...X7 | FPGA Bank 1A, U6 |
HSIO, HI, HO | B2B, J11
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JTAG Interface
JTAG access to the attached SoM through B2B connector JB2. The JTAG Enable is connected to VCC and after power on it will be enable.
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Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - |Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
* TBD - To Be Determined
Power Distribution Dependencies
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TEB0707_PWR_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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Scroll Only |
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![](/download/attachments/105698014/TEB0707_PWR_PD.png?version=3&modificationDate=1603983130310&api=v2)
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Power-On Sequence
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draw.io Diagram |
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border | false |
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diagramName | TEB0707_OV_MC |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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draw.io Diagram |
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border | false |
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diagramName | TEB0707_PWR_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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