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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfaceI/O Signal CountConnected toNotes
JB1


Ethernet LAN8x Single ended, 4x Diff pairsRJ45 Socket, J2
SD  Card6 x Single EndedIO Expander, U4
I/Os20x Single EndedFPGA BAnk 6, U6
CRUVI

20x Single ended, 10x Diff pairs

4x Single Ended

High Speed CRUVI, J12CRUVI C
Control Signals5x Single EndedFPGA, U6
I/Os8x Single endedFPGA Bank 8, U6
VBAT1x Single EndedPin Header, J3
JB2

CRUVI

8x Single ended, 4x Diff pairs

4x Single Ended

High Speed CRUVI, J10CRUVI A
CRUVI12x Single ended, 6x Diff pairsHigh Speed CRUVI, J11CRUVI B
JTAG4x Single EndedFPGA Bank 5, U6
JB3CRUVI

12x Single ended, 6x Diff pairs

4x Single Ended

High Speed CRUVI, J11CRUVI B
USB 4x Single EndedUSB A, J9


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Scroll Title
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titleCRUVI B2B connectors information

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SpeedDesignatorsSchematicConnected toNotes
High

J12VCCIO_CCB2B, J11GPIO
CC_SMBB2B, J11SC SPI
J11A_X6...7B2B, J11I2C0 SDA/SCL
B_X0...7|B2B, J11GPIO



CRUVI C, J12A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1

MODE

REFCLK

FPGA Bank 8, U6

SMB_ALERT

SMB_SDA

SMB_SCL

FPGA Bank 8, U6
DI,DO,SCK,SELFPGA Bank 8, U6
HSIO, HI, HOB2B, JB1
RESET B2B, JB1
High









CRUVI B, J11A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1

MODE

REFCLK

FPGA Bank 3, U6

SMB_ALERT

SMB_SDA

SMB_SCL

FPGA Bank 2, U6
DI,DO,SCK,SELFPGA Bank 2, U6
HSIO, HI, HOB2B, JB3
RESET B2B, JB3
High



CRUVI A,
J10C_X0...7B2B, J11GPIOLow
J13



A0...A5 (N/P)B2B,
J11
JB2
B0...B5 (N/P)B2B,
J11
JB2

MODE

B2B, J11RESET

REFCLK

FPGA Bank 2, U6
B2B, J11

SMB_ALERT

SMB_SDA

SMB_SCL

B2B
FPGA Bank 3,
J11
U6
DI,DO,SCK,SEL
B2B, J11SPI
FPGA Bank 2, U6
HSIO, HI, HOB2B, JB2
RESET B2B, JB2
LowCRUVIX0...X7FPGA Bank 1A, U6
HSIO, HI, HOB2B, J11



JTAG Interface

JTAG access to the attached SoM through B2B connector JB2. The JTAG Enable is connected to VCC and after power on it will be enable.

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • |Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorTable_PWR_PC
titlePower Consumption

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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Scroll Title
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titlePower Distribution
2
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Scroll Only


Power-On Sequence

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