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Scroll Title |
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anchor | Table_SIP_ETH |
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title | RJ45 LAN Socket information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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2 | PHY_MDI0_P | B2B, JB1 |
| 3 | PHY_MDI0_N | B2B, JB1 |
| 4 | PHY_MDI1_P | B2B, JB1 |
| 5 | PHY_MDI1_N | B2B, JB1 |
| 6 | PHY_MDI2_P | B2B, JB1 |
| 7 | PHY_MDI2_N | B2B, JB1 |
| 8 | PHY_MDI3_P | B2B, JB1 |
| 9 | PHY_MDI3_N | B2B, JB1 |
| VCC | ETH-VCC | B2B, JB1 |
| Green LED | ETH1_LED0 | Intel MAX 10, U6 | Link/Activity indicator | Yellow LED | ETH1_LED1 | Intel MAX 10, U6 | Speed indicator |
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Jumpers
There are three Jumpers provided to choose the CRUVI Extension power supply.
Scroll Title |
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anchor | Table_SIP_Jumpers |
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title | Jumpers information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Connected to | Notes |
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J14 | VCCIO_CC | B2B, JB2 | CRUVI C | J16 | VCCIO_CB | B2B, JB2 | CRUVI B | J17 | VCCIO_CA | B2B, JB2 | CRUVI A |
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Scroll Title |
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anchor | Table_SIP_SMD |
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title | Jumpers information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Connected to | Notes |
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J3 | VBAT | B2B, JB1 |
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Test Points
Page properties |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Intel MAX 10 | U6 |
| FTDI | U8 | SDIO Expander | U4 | EEPROM | U10 | Oscillator | U7 | LEDs | D1...8U8 |
| SDIO Expander | U4 |
| EEPROM | U10 |
| Oscillator | U7 |
| LEDs | D1...8 |
| DIP Switch | S1 |
| Push Buttons | S2, S3 |
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FTDI FT2232H
The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.
Scroll Title |
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anchor | Table_OBP_FT2232H |
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title | FTDI chip interfaces and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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ADBUS0 | TCK | FPGA Bank 1B, U6 | JTAG interface | ADBUS1 | TDI | FPGA Bank 1B, U6 | ADBUS2 | TDO | FPGA Bank 1B, U6 | ADBUS3 | TMS | FPGA Bank 1B, U6 | BDBUS0 | F_UART_TX | FPGA Bank 1B, U6 | UART Transmitter output | BDBUS1 | F_UART_RX | FPGA Bank 1B, U6 | UART Receiver Input | OSCI | OSCI | Oscillator, U7 | Clock 12 MHz | EECS | EECS | EEPROM, U10 | EEPROM Contains FTDI configuration | EECLK | EECLK | EEPROM, U10 | EEDATA | EEDATA | EEPROM, U10 | DM/DP | FD_N/ FD_P | Micro USB, J15 | USB to UART | nRESET | 3.3V | 3.3V |
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LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Schematic | Connected to | Active Level | Note |
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D2 | Green | LED3 | FPGA Bank 3 | Active High |
| D3 | Green | LED5 | FPGA Bank 3 | Active High |
| D4 | Green | LED7 | FPGA Bank 3 | Active High |
| D5 | Green | LED4 | FPGA Bank 8 | Active High |
| D6 | Green | LED6 | FPGA Bank 2 | Active High |
| D7 | Green | LED8 | FPGA Bank 8 | Active High |
| D8 | Green | LED2 | FPGA Bank 8 | Active High |
| D9 | Green | LED1 | FPGA Bank 8 | Active High |
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Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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draw.io Diagram |
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border | true |
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| |
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diagramName | TEB0707_PWR_DP |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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| scroll-ignore
Scroll Only |
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![](/download/attachments/105698014/TEB0707_PWR_PD.png?version=3&modificationDate=1603983130310&api=v2)
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Power-On Sequence
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