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Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Intel Max10 CPLD
The TEB0707 is quipped with an Intel Max10 as CPLD with the ability of Levelshifting of CRUVI connectors, JTAG/UART forward to modules, Module control pis, power sequencing and IO voltage selection along with providing User Push buttons, LEDs and switches. For complete information, please see the TEB0707 MAX10 CPLD.
FTDI FT2232H
The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG.
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Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Schematic | Connected to | Active Level | Note |
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D2 | Green | LED3 | FPGA Bank 3 | Active High |
| D3 | Green | LED5 | FPGA Bank 3 | Active High |
| D4 | Green | LED7 | FPGA Bank 3 | Active High |
| D5 | Green | LED4 | FPGA Bank 8 | Active High |
| D6 | Green | LED6 | FPGA Bank 2 | Active High |
| D7 | Green | LED8 | FPGA Bank 8 | Active High |
| D8 | Green | LED2 | FPGA Bank 8 | Active High |
| D9 | Green | LED1 | FPGA Bank 8 | Active High |
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EEPROM
The EEPROM IC, U8 contains the FTDI configuration.
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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CS | EECS | FTDI, U8 |
| CLK | EECLK | FTDI, U8 |
| DIN | EEDATA | FTDI, U8 |
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Scroll Title |
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DIP Switch
There is a DIP Switch provided for direct user controlling and setting of boot mode, programming mode, enable and JTAG selection.
Scroll Title |
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anchor | anchor | Table_OBP_I2C_EEPROMDIP |
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title | I2C address for EEPROMDIP Switch connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C AddressDesignator |
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DIP1 | PROGMODE | Programming mode | select between CPLD (low, closed, on) on SoM or FPGA/SoC (high, open, off ) | DIP2 | MODE | Boot Mode | select SD boot mode when card installed ('low'), else QSPI ('high') | DIP3 | EN1 | Power Enable | module power always enabled | DIP4 | TAGEN | JTAG Selection | JTAG mode between CPLD or SoM |
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Push Buttons
Scroll Title |
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anchor | Table_OBP_BTN |
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title | Push Buttons informations |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Function | Notes |
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S2 | RESET | SoM Reset |
| S3 | BUTTON1 | User Button |
A0 | U10
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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U7 | MEMS Oschilator | 12 MHz |
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