2020.2 | needed, Vivado is included into Vitis installation |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title | Hardware Modules |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0808-ES1 | es1_2gb | REV03|REV02 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-ES2 | es2_2gb | REV04|REV03 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-2ES2 | 2es2_2gb | REV04|REV03 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-04-09EG-1EA | 9eg_1e_2gb | REV04 | 2GB | 64MB | NA | NA |
| TE0808-04-09EG-1EB | 9eg_1e_4gb | REV04 | 4GB | 64MB | NA | NA |
| TE0808-04-09EG-1ED | 9eg_1e_4gb | REV04 | 4GB | 64MB | NA | 1 mm connectors |
| TE0808-04-09EG-2IB | 9eg_2i_4gb | REV04 | 4GB | 64MB | NA | NA |
| TE0808-04-15EG-1EB | 15eg_1e_4gb | REV04 | 4GB | 64MB | NA | NA |
| TE0808-04-09EG-1EE | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-09EG-1EL | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors |
| TE0808-04-09EG-2IE | 9eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-15EG-1EE | 15eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-06EG-1EE | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-06EG-1E3 | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors |
| TE0808-04-6GI21-L | 6eg_2i_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors |
| TE0808-04-6GI21-A | 6eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-6BI21-A | 6eg_1i_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-9GI21-A | 9eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-9BE21-A | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-6BE21-L | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors |
| TE0808-04-6BE21-A | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-9BE21-L | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors |
| TE0808-04-BBE21-A | 15eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA |
| TE0808-04-6BI21-X | 6eg_1i_4gb | REV04 | 4GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-6BE21-L | 6eg_1e_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-05-6BE21-A | 6eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-6BI21-D | 6eg_1i_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | SoC without encryption | TE0808-05-6BI21-X | 6eg_1i_4gb | REV05 | 4GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-6BI41-X | 6eg_1i_8gb | REV05 | 8GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-9BE21-A | 9eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-9BE21-L | 9eg_1e_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-05-9BI41-X | 9eg_1i_8gb | REV05 | 8GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-9GI21-A | 9eg_2i_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-9GI21-C | 9eg_2i_4gb | REV05 | 4GB | 128MB | NA | NA | SoC without encryption | TE0808-05-BBE21-A | 15eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-BBE21-L | 15eg_1e_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | NA |
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Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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anchor | Table_HWC |
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title | Hardware Carrier |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Carrier Model | Notes |
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Custom PCB | use simple Board Part files, if MIO connected is different to TEBF0808 | TEBF0808 | Used as reference carrier. | TEBT0808-01 | Change UART0 to UART1 (MIO68...69) and regenerate design |
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Additional HW Requirements:
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anchor | Table_AHW |
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title | Additional Hardware |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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--- | --- |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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anchor | Table_DS |
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title | Design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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anchor | Table_ADS |
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title | Additional design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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--- | --- | --- |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title | Prebuilt files |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Source | *.scr | Distro Boot file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image Modified - Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
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Note: - Programming and Startup procedure
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device,
Usage
QSPI Boot:
- Prepare HW like described on section 71631051
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
System Design - Vivado
Block Design
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anchor | Figure_BD |
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title | Block Design |
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Image Modified |
PS Interfaces
Activated interfaces:
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anchor | Table_PSI |
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title | PS Interfaces |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Note |
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DDR |
| QSPI | MIO | UART0 | MIO, please select other one, if you have connected uart to second controller or other MIO | SWDT0..1 |
| TTC0..3 |
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Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified |