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Template Revision 3.1 Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" - Change List 3.0 to 3.1
- Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- Change List 2.9 to 3.0
- add fix table of content
- add table size as macro
- removed page initial creator
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.
Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
Key Features
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- Vitis/Vivado 2020.2
- QSPI
- Custom Carrier (minimum PS Design with available module components only)
- Modified FSBL (some additional outputs only)
- Special FSBL for QSPI Programming
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Revision History
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- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2021-05-12 | 2020.2 | TE0808-test_board-vivado_2020.2-build_5_20210512133121.zip TE0808-test_board_noprebuilt-vivado_2020.2-build_5_20210512133137.zip | John Hartfiel | | 2021-02-05 | 2020.2 | TE0808-test_board-vivado_2020.2-build_0_20210204141911.zip TE0808-test_board_noprebuilt-vivado_2020.2-build_1_20210204142855.zip | John Hartfiel | | 2020-09-29 | 2019.2 | TE0808-test_board_noprebuilt-vivado_2019.2-build_15_20200929070740.zip TE0808-test_board-vivado_2019.2-build_15_20200929070725 | John Hartfiel | | 2020-09-22 | 2019.2 | TE0808-test_board_noprebuilt-vivado_2019.2-build_14_20200922073159.zip TE0808-test_board-vivado_2019.2-build_14_20200922073144.zip | John Hartfiel | | 2020-03-25 | 2019.2 | TE0808-test_board_noprebuilt-vivado_2019.2-build_8_20200325083246.zip TE0808-test_board-vivado_2019.2-build_8_20200325083204.zip | John Hartfiel | | 2020-01-22 | 2019.2 | TE0808-test_board_noprebuilt-vivado_2019.2-build_3_20200122142231.zip TE0808-test_board-vivado_2019.2-build_3_20200122142208.zip | John Hartfiel | - 2019.2 update
- Vitis support
| 2019-08-09 | 2018.3 | TE0808-test_board_noprebuilt-vivado_2018.3-build_07_20190809131546.zip TE0808-test_board-vivado_2018.3-build_07_20190809131522.zip | John Hartfiel | | 2019-05-06 | 2018.3 | TE0808-test_board_noprebuilt-vivado_2018.3-build_05_20190507124141.zip TE0808-test_board-vivado_2018.3-build_05_20190507124130.zip | John Hartfiel | | 2018-07-11 | 2018.2 | TE0808-test_board_noprebuilt-vivado_2018.2-build_02_20180711143743.zip TE0808-test_board-vivado_2018.2-build_02_20180711143702.zip | John Hartfiel | - additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-03-29 | 2017.4 | TE0808-test_board-vivado_2017.4-build_07_20180329151341.zip TE0808-test_board_noprebuilt-vivado_2017.4-build_07_20180329151355.zip | John Hartfiel | | 2018-01-16 | 2017.4 | TE0808-test_board-vivado_2017.4-build_04_20180116144644.zip TE0808-test_board_noprebuilt-vivado_2017.4-build_04_20180116144657.zip | John Hartfiel | - Update Board Part for TEBF0808
- no changes for test board design and minimal board parts
| 2018-01-15 | 2017.4 | TE0808-test_board-vivado_2017.4-build_03_20180115084954.zip TE0808-test_board_noprebuilt-vivado_2017.4-build_03_20180115085020.zip | John Hartfiel | | 2017-12-20 | 2017.2 | TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip | John Hartfiel | | 2017-11-22 | 2017.2 | TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip | John Hartfiel | - Update Board Part CSV File
- Regenerate design
| 2017-11-16 | 2017.2 | TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip | John Hartfiel | - Update Board Part CSV File with new Flash assembly variants
| 2017-11-13 | 2017.2 | TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip | John Hartfiel | |
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Release Notes and Know Issues
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vitis | 2020.2 | needed, Vivado is included into Vitis installation |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0808-ES1 | es1_2gb | REV03|REV02 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-ES2 | es2_2gb | REV04|REV03 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-2ES2 | 2es2_2gb | REV04|REV03 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0808-04-09EG-1EA | 9eg_1e_2gb | REV04 | 2GB | 64MB | NA | NA | NA | TE0808-04-09EG-1EB | 9eg_1e_4gb | REV04 | 4GB | 64MB | NA | NA | NA | TE0808-04-09EG-1ED | 9eg_1e_4gb | REV04 | 4GB | 64MB | NA | 1 mm connectors | NA | TE0808-04-09EG-2IB | 9eg_2i_4gb | REV04 | 4GB | 64MB | NA | NA | NA | TE0808-04-15EG-1EB | 15eg_1e_4gb | REV04 | 4GB | 64MB | NA | NA | NA | TE0808-04-09EG-1EE | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-09EG-1EL | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-04-09EG-2IE | 9eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-15EG-1EE | 15eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-06EG-1EE | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-06EG-1E3 | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-04-6GI21-L | 6eg_2i_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | TE0808-04-6GI21-A | NA | 6eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA | TE0808-04-6BI21-A | 6eg_1i_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-9GI21-A | 9eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-9BE21-A | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-6BE21-L | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-04-6BE21-A | 6eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-9BE21-L | 9eg_1e_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-04-BBE21-A | 15eg_1e_4gb | REV04 | 4GB | 128MB | NA | NA | NA | TE0808-04-6BI21- | XX | 6eg_1i_ | 4gb4gb | REV04 | 4GB4GB | 128MB128MB | NANA | NANA | U41 replaced with schottky | diodesdiodes | TE0808-05-6BE21-L | 6eg_1e_4gb | REV05 REV05 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-05-6BE21-A | 6eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-6BI21-D | 6eg_1i_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | SoC without encryption | TE0808-05-6BI21-X | 6eg_1i_4gb | REV05 | 4GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-6BI41-X | 6eg_1i_8gb | REV05 | 8GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-9BE21-A | 9eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-9BE21-L | 9eg_1e_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0808-05-9BI41-X | 9eg_1i_8gb | REV05 | 8GB | 128MB | NA | NA | U41 replaced with schottky diodes | TE0808-05-9GI21-A | 9eg_2i_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-9GI21-C | 9eg_2i_4gb | REV05 | 4GB | 128MB | NA | NA | SoC without encryption | TE0808-05-BBE21-A | 15eg_1e_4gb | REV05 | 4GB | 128MB | NA | NA | NA | TE0808-05-BBE21-L | 15eg_1e_4gb | REV05 | 4GB | 128MB | NA | 1 mm connectors | NA |
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Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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Carrier Model | Notes |
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Custom PCB | use simple Board Part files, if MIO connected is different to TEBF0808 | TEBF0808 | Used as reference carrier. | TEBT0808-01 | Change UART0 to UART1 (MIO68...69) and regenerate design |
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Additional HW Requirements:
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Additional Hardware | Notes |
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--- | --- |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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Type | Location | Notes |
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--- | --- | --- |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Source | *.scr | Distro Boot file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device,
Usage
QSPI Boot:
- Prepare HW like described on section 71631051
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
System Design - Vivado
Block Design
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PS Interfaces
Activated interfaces:
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title | PS Interfaces |
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Type | Note |
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DDR |
| QSPI | MIO | UART0 | MIO, please select other one, if you have connected uart to second controller or other MIO | SWDT0..1 |
| TTC0..3 |
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Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2020.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2020.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2020.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2020.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | Authors | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| | 2021-02-05 | v.33 | John Hartfiel | - Release 2020.2
- Document Style update
| 2021-02-05 | v.31 | John Hartfiel | | 2020-03-25 | v.28 | John Hartfiel | | 2020-01-27 | v.27 | John Hartfiel | | 2020-01-22 | v.26 | John Hartfiel | - new assembly variants
- Release 2019.2
| 2019-08-09 | v.24 | John Hartfiel | - new assembly variants
- small document style update
| 2019-05-07 | v.22 | John Hartfiel | | 2018-07-11 | v.21 | John Hartfiel | | | v.20 | John Hartfiel | | 2018-02-08 | v.19 | John Hartfiel | | 2017-12-20 | v.14 | John Hartfiel | - Design Update
- typo correction on documentation
| 2017-11-22 | v.10 | John Hartfiel | - Update assembly versions with new Flash size
- Udate HW Table Name
- Update Design
| 2017-11-14 | v.6 | John Hartfiel | | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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