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Overview

The Trenz Electronic TE0820 is a powerful 4 x 5 cm industrial/extended module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 8 Gb DDR4 SDRAM chip, up to 64 Gb eMMC chip,  2x 512 Mb flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs. Additionally the module provides Gigabit Ethernet and USB2.0 Transceivers.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.

Key Features

• SoC/FPGA
  
  • Package: SFVC784
  • Device: ZU2 ...ZU5, *
  • Engine:  EG, CG, EV, *
  • Speed: -1, -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **
• RAM/Storage
  • 2x  DDR4 SDRAM,
    • Data Width: 16 Bit
    • Size: 8 Gb, *
    • Speed: 2400 Mbps, ***
  • 2x QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x e.MMC Memory
    • Data Width: 16 Bit
    • Size: 8 Gb, *
  • MAC address serial EEPROM
• On Board
  
  • Lattice MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1 Gbps RGMII Ethernet interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • Graphic Processor Mali-400 MP2, *
  • 156 x High Performance (HP) und 96 x High Density PL I/Os
  • 4 x serial PS GTR transceivers
    • PCI Express interface
    • SATA 3.1 interface

    • DisplayPort interface with video resolution up to 4k x 2k

    • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
• Power
  • All power regulators on board
• Dimension
  • 40 x 50 mm
• Note
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination
  • Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. Xilinx Zynq UltraScale+ MPSoC, U1
2. 1.8V, 512 Mbit QSPI flash memory, U7
3. 1.8V, 512 Mbit QSPI flash memory, U17
4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
11. 8 GByte eMMC memory, U6
12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
13. I2C programmable, any  frequency , any output  quad clock generator, U10
14. Highly integrated full featured hi-speed USB 2.0 ULPItransceiver, U18
15. LED D1(Red) Done Pin
16. LED D2 (Green) CPLD Status, User LED
    
17. LED D3 (Red) PS Error
    
18. LED D4 (Green) PS Error Status
    

Initial Delivery State

Configuration Signals

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

I2C Addresses

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

MIOs

Test Points

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module.

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Please check the entire information at TE0820 CPLD.

See also TE0820 System Controller CPLD page.

eMMC Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

DDR4 Memory

The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

• Part number: K4A8G165WB-BIRC
• Supply voltage: 1.2V
• Speed: 2400 Mbps
• Temperature: -40 ~ 95 °C

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHY

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

EEPROM

There is a 2Kb EEPROM (U25) provided on the module TE0820.

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Clock Sources

LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

 * TBD - To Be Determined soon with reference design setup.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.

Power-On Sequence

The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out  is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm

• PCB thickness: 1.6 mm

• Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Currently Offered Variants 

Revision History

Hardware Revision History

Document Change History

Table 21: Document change history

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