The Trenz Electronic TE0820 is a powerful 4 x 5 cm industrial/extended module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 8 Gb DDR4 SDRAM chip, up to 64 Gb eMMC chip, 2x 512 Mb flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs. Additionally the module provides Gigabit Ethernet and USB2.0 Transceivers.
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.
- Package: SFVC784
- Device: ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **
- 2x DDR4 SDRAM,
- Data Width: 16 Bit
- Size: 8 Gb, *
- Speed: 2400 Mbps, ***
- 2x QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x e.MMC Memory
- Data Width: 16 Bit
- Size: 8 Gb, *
- MAC address serial EEPROM
- 2x DDR4 SDRAM,
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
- 1 Gbps RGMII Ethernet interface
- Hi-speed USB2 ULPI transceiver with full OTG support
- Graphic Processor Mali-400 MP2, *
- 156 x High Performance (HP) und 96 x High Density PL I/Os
- 4 x serial PS GTR transceivers
- PCI Express interface
- SATA 3.1 interface
DisplayPort interface with video resolution up to 4k x 2k
- 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
- All power regulators on board
- 40 x 50 mm
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
Additional assembly options are available for cost or performance optimization upon request.
- Xilinx Zynq UltraScale+ MPSoC, U1
- 1.8V, 512 Mbit QSPI flash memory, U7
- 1.8V, 512 Mbit QSPI flash memory, U17
- 8 Gbit (512 x 16) DDR4 SDRAM, U2
- 8 Gbit (512 x 16) DDR4 SDRAM, U3
- Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-130, JM3
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
- I2C programmable, any frequency , any output quad clock generator, U10
- Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
- LED D1(Red) Done Pin
- LED D2 (Green) CPLD Status, User LED
- LED D3 (Red) PS Error
- LED D4 (Green) PS Error Status
Initial Delivery State
Storage device name
Dual QSPI Flash Memory
|DDR4 SDRAM||Not programmed|
|Programmable Clock Generator||Not programmed|
|CPLD (LCMXO2-256HC)||Programmed||TE0820 CPLD|
Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.
*changable also with other CPLD Firmware: TE0820 CPLD
|JM1-28||Input||CPLD Enable Pin|
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
Zynq MPSoC's I/O banks signals connected to the B2B connectors:
I/O Signal Count
48x Single Ended, 24x LVDS Pairs
|Max voltage 1.8V|
2x Single Ended
|Max voltage 1.8V|
18x Single Ended, 9x LVDS Pairs
|Max voltage 1.8V|
16x Single Ended, 8x LVDS Pairs
|Max voltage 1.8V|
48x Single Ended, 24x LVDS Pairs
|Max voltage 1.8V|
|500||MIO||JM1||8x Single Ended||1.8V|
6x Single Ended
16x Single Ended, 8x LVDS Pairs
1x differential Clock
For detailed information about the pin-out, please refer to the Pin-out table.
The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
|Lane||Bank||Signal Name||B2B Pin||Note|
There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
|Clock signal||Bank||Connected to||Notes|
|B505_CLK0_P||505||B2B, JM3-31||Supplied by the carrier board|
|B505_CLK0_N||505||B2B, JM3-33||Supplied by the carrier board|
|B505_CLK1_P||505||U10, CLK2A||On-board Si5338A|
|B505_CLK1_N||505||U10, CLK2B||On-board Si5338A|
|B505_CLK3_P||505||U10, CLK1A||On-board Si5338A|
|B505_CLK3_N||505||U10, CLK1B||On-board Si5338A|
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
B2B Connector Pin
|JTAGEN||JM1-89||Pulled Low: Xilinx Zynq UltraScale+ MPSoC|
Pulled High: Lattice MachXO CPLD
Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.
On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:
|I2C Device||I2C Address||Notes|
PLL Clock Generator, U10
|MIO Pin||Connected to||B2B||Notes|
|0...5||QSPI Flash, U7||-||SPI Flash|
|7...12||QSPI Flash, U17||-||SPI Flash|
|24||ETH Transceiver, U8||-||ETH_RST|
|25||USB2.0 Transceiver, U18||-||OTG_RST|
|52...63||USB2.0 Transceiver, U18||-|
|63...77||Ethernet Transceiver, U8||-|
|Test Point||Signal||Connected to||Notes|
|1||PS_LP0V85||Voltage Regulator, U12|
|2||DDR_2V5||Voltage Regulator, U4|
|3||PS_AVCC||Voltage Regulator, U9|
|4||DDR_1V2||Voltage Regulator, U15|
|5||PS_AVTT||Voltage Regulator, U3|
|7||PS_FP0V85||Voltage Regulator, U26|
|10||PS_PLL||Voltage Regulator, U23|
|11||PL_VCCINT||Voltage Regulator, U5|
|15||PL_VCCINT_IO||Voltage Regulator, U27|
|16||PL_VCU||Voltage Regulator, U24|
System Controller CPLD
The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module.
Special purpose pins are connected to System Controller CPLD and have following default configuration:
|Pin Name||Mode||Function||Default Configuration|
No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management
|PGOOD||Output||Power Good||Only indirect used for power status, see CPLD description|
|NOSEQ||-||-||No used for Power sequencing, see CPLD description|
Active low reset, gated to POR_B
|JTAGEN||Input||JTAG Select||Low for normal operation, high for CPLD JTAG access|
Please check the entire information at TE0820 CPLD.
See also TE0820 System Controller CPLD page.
eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB-BIRC
- Supply voltage: 1.2V
- Speed: 2400 Mbps
- Temperature: -40 ~ 95 °C
Quad SPI Flash Memory
Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).
|PHY Pin||ZYNQ Pin||B2B Name||Notes|
|ULPI||MIO52..63||-||Zynq USB0 MIO pins are connected to the USB PHY.|
|REFCLK||-||-||52.000000 MHz from on-board oscillator (U14).|
|REFSEL[0..2]||-||-||Reference clock frequency select, all set to GND selects 52.000000 MHz.|
|RESETB||MIO25||-||Active low reset.|
|CLKOUT||MIO52||-||Connected to 1.8V, selects reference clock operation mode.|
|DP, DM||-||OTG_D_P, OTG_D_N||USB data lines routed to B2B connector JM3 pins 47 and 49.|
|CPEN||-||VBUS_V_EN||External USB power switch active high enable signal, routed to JM3 pin 17.|
|VBUS||-||USB_VBUS||Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.|
|ID||-||OTG_ID||For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.|
There is a 2Kb EEPROM (U25) provided on the module TE0820.
|MIO Pin||Schematic||U25 Pin||Notes|
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.
A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
|U25 Pin||Signal||Connected to||Direction||Note|
|CLK1||B505_CLK3||FPGA Bank 505||IN|
|CLK2||B505_CLK1||FPGA Bank 505||IN|
|U32||MEMS Oscillator||33.33 MHz|
|U11||MEMS Oscillator||25 MHz|
|U14||MEMS Oscillator||52 MHz|
|Designator||Color||Connected to||Active Level||Note|
Power and Power-on Sequence
Power supply with minimum current capability of 3A for system startup is recommended.
|Power Input Pin||Typical Current|
* TBD - To Be Determined soon with reference design setup.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Power Distribution Dependencies
See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.
The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.
|Power Rail Name on B2B Connector||JM1 Pins||JM2 Pins||Direction||Notes|
1, 3, 5
|2, 4, 6, 8||Input||Supply voltage from the carrier board|
|3.3V||-||10, 12||Output||Internal 3.3V voltage level|
|3.3VIN||13, 15||-||Input||Supply voltage from the carrier board|
|1.8V||39||-||Output||Internal 1.8V voltage level|
|JTAG VREF||-||91||Output||JTAG reference voltage.|
Attention: Net name on schematic is "3.3VIN"
|VCCO_64||-||7, 9||Input||High performance I/O bank voltage|
|VCCO_65||-||5||Input||High performance I/O bank voltage|
|VCCO_66||9, 11||-||Input||High performance I/O bank voltage|
|Bank 24 HD||VCCO_HD24_24||Variable||Max voltage 3.3V|
|Bank 25 HD||Variable||Max voltage 3.3V|
|Bank 26 HD||VCCO_HD25_26||Variable||Max voltage 3.3V|
|Bank 44 HD||VCCO_HD24_44||Variable||Max voltage 3.3V|
|Bank 64 HP||VCCO_64||N.C||Not Connected|
|Bank 65 HP|
|Variable||Max voltage 1.8V|
|Bank 66 HP||VCCO_66||1.8V|
|Bank 500 PSMIO||VCCO_PSIO0_500||1.8V|
Bank 501 PSMIO
|Bank 502 PSMIO||VCCO_PSIO2_502||1.8V|
|Bank 503 PSCONFIG||VCCO_PSIO3_503||1.8V|
|Bank 504 PSDDR||DDR_1V2||1.2V|
Board to Board Connectors
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
- 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
- 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
|Order number||Connector on baseboard||compatible to||Mating height|
The module can be manufactured using other connectors upon request.
Connector Speed Ratings
The LSHM connector speed rating depends on the stacking height; please see the following table:
|Stacking height||Speed rating|
|12 mm, Single-Ended||7.5 GHz / 15 Gbps|
|12 mm, Differential|
6.5 GHz / 13 Gbps
|5 mm, Single-Ended||11.5 GHz / 23 Gbps|
|5 mm, Differential||7.0 GHz / 14 Gbps|
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
|PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report||07 04, 2016 by Thorsten Trenz|
|PDF File lshm_dv.pdf LSHM catalog page||07 04, 2016 by Thorsten Trenz|
|PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing||07 04, 2016 by Thorsten Trenz|
|PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing||07 04, 2016 by Thorsten Trenz|
|PDF File REF-189016-01.pdf Technical Drawing||07 04, 2016 by Thorsten Trenz|
|PDF File REF-189016-02.pdf Technical Drawing||07 04, 2016 by Thorsten Trenz|
|PDF File REF-189017-01.pdf Technical Drawing||07 04, 2016 by Thorsten Trenz|
|PDF File REF-189017-02.pdf Technical Drawing||07 04, 2016 by Thorsten Trenz|
|PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report||07 04, 2016 by Thorsten Trenz|
|PDF File tc0929--2611_qua(1).pdf Shock and vibration report||07 04, 2016 by Thorsten Trenz|
Absolute Maximum Ratings
VIN supply voltage
|See EN6347QI and TPS82085SIL datasheets|
|3.3VIN supply voltage||-0.1||3.630||V||Xilinx DS925 and TPS27082L datasheet|
|PS I/O supply voltage, VCCO_PSIO||-0.5||3.630||V||Xilinx document DS925|
|PS I/O input voltage||-0.5||VCCO_PSIO + 0.55||V||Xilinx document DS925|
|HP I/O bank supply voltage, VCCO||-0.5||2.0||V||Xilinx document DS925|
|HP I/O bank input voltage||-0.55||VCCO + 0.55||V||Xilinx document DS925|
|PS GTR reference clocks absolute input voltage||-0.5||1.1||V||Xilinx document DS925|
|PS GTR absolute input voltage||-0.5||1.1||V||Xilinx document DS925|
Voltage on SC CPLD pins
|Lattice Semiconductor MachXO2 datasheet|
|See eMMC datasheet|
Recommended Operating Conditions
|VIN supply voltage||3.3||6||V||See TPS82085S datasheet|
|3.3VIN supply voltage||3.3||3.465||V||See LCMXO2-256HC, Xilinx DS925 datasheet|
|PS I/O supply voltage, VCCO_PSIO||1.710||3.465||V||Xilinx document DS925|
|PS I/O input voltage||–0.20||VCCO_PSIO + 0.20||V||Xilinx document DS925|
|HP I/O banks supply voltage, VCCO||0.950||1.9||V||Xilinx document DS925|
|HP I/O banks input voltage||-0.20||VCCO + 0.20||V||Xilinx document DS925|
|Voltage on SC CPLD pins||-0.3||3.6||V||Lattice Semiconductor MachXO2 datasheet|
|Operating Temperature Range||0||85||°C||Xilinx document DS925, extended grade Zynq temperarure range|
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
Currently Offered Variants
Hardware Revision History
Document Change History
Pedram Babakhani , Ali Naseri , Antti Lukats , John Hartfiel , Jan Kumann , Martin Rohrmüller , Susanne Kunath
Table 21: Document change history
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