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Overview

The Trenz Electronic TE0820 is a powerful 4 x 5 cm industrial/extended module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 8 Gb DDR4 SDRAM chip, up to 64 Gb eMMC chip,  2x 512 Mb flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs. Additionally the module provides Gigabit Ethernet and USB2.0 Transceivers.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.

Key Features


  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2 ...ZU5, *
    • Engine:  EG, CG, EV, *
    • Speed: -1, -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **
  • RAM/Storage
    • 2x  DDR4 SDRAM,
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      • Speed: 2400 Mbps, ***
    • 2x QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x e.MMC Memory
      • Data Width: 16 Bit
      • Size: 8 Gb, *
    • MAC address serial EEPROM
  • On Board
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • Interface
    • 1 Gbps RGMII Ethernet interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • Graphic Processor Mali-400 MP2, *
    • 156 x High Performance (HP) und 96 x High Density PL I/Os
    • 4 x serial PS GTR transceivers
      • PCI Express interface
      • SATA 3.1 interface
      • DisplayPort interface with video resolution up to 4k x 2k

      • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • Power
    • All power regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram


TE0820-03 block diagram

Main Components

TE0820-03 main components
  1. Xilinx Zynq UltraScale+ MPSoC, U1
  2. 1.8V, 512 Mbit QSPI flash memory, U7
  3. 1.8V, 512 Mbit QSPI flash memory, U17
  4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
  5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
  6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
  8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
  11. 8 GByte eMMC memory, U6
  12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
  13. I2C programmable, any  frequency , any output  quad clock generator, U10
  14. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
  15. LED D1(Red) Done Pin
  16. LED D2 (Green) CPLD Status, User LED
  17. LED D3 (Red) PS Error
  18. LED D4 (Green) PS Error Status

Initial Delivery State

Storage device name

Content

Notes

Dual QSPI Flash Memory

Not programmed


eMMC Memory

Not programmed


DDR4 SDRAMNot programmed
Programmable Clock GeneratorNot programmed
CPLD (LCMXO2-256HC)ProgrammedTE0820 CPLD
Initial delivery state of programmable devices on the module

Configuration Signals

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

MODE Pin

Boot Mode
High

QSPI*

LowSD Card*

*changable also with other CPLD Firmware: TE0820 CPLD

Boot process.

Signal

B2BI/ONote

EN1

JM1-28InputCPLD Enable Pin
RESINJM2-18InputGeneral Reset
Reset process.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

BankType

B2B Connector

I/O Signal Count

VoltageNotes

64

HP

JM2

48x Single Ended, 24x  LVDS Pairs

Variable

Max voltage 1.8V

64

HP

JM2

2x Single Ended

Variable

Max voltage 1.8V
65

HP

JM2

18x Single Ended, 9x  LVDS Pairs

Variable

Max voltage 1.8V

65

HP

JM3

16x Single Ended, 8x  LVDS Pairs

Variable

Max voltage 1.8V

66

HP

JM1

48x Single Ended, 24x  LVDS Pairs

Variable

Max voltage 1.8V
500MIOJM18x Single Ended1.8V

501

MIO

JM1

6x Single Ended

3.3V


505

GTR

JM3

16x Single Ended, 8x  LVDS Pairs

-

4x Lanes

505

GTR CLK

JM3

1x differential Clock

-


General PL I/O to B2B connectors information

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankSignal NameB2B PinNote
0505
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27

1505
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21

2505
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15

3505
  • B505_RX3_P
  • B505_RX3_N
  • B505_TX3_P
  • B505_TX3_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9

MGT Lanes connection

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Clock signalBankConnected toNotes
B505_CLK0_P505B2B, JM3-31Supplied by the carrier board
B505_CLK0_N505B2B, JM3-33Supplied by the carrier board
B505_CLK1_P505U10, CLK2AOn-board Si5338A
B505_CLK1_N505U10, CLK2BOn-board Si5338A
B505_CLK2_P505N/ANot connected
B505_CLK2_N505N/ANot connected
B505_CLK3_P505U10, CLK1AOn-board Si5338A
B505_CLK3_N505U10, CLK1BOn-board Si5338A
MGT Clock Sources Information

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

JTAG Signal

B2B Connector Pin

Notes
TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99 
JTAGENJM1-89Pulled Low: Xilinx Zynq UltraScale+ MPSoC
Pulled High: Lattice MachXO CPLD
JTAG pins connection

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

I2C Addresses

On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:

I2C DeviceI2C AddressNotes

PLL Clock Generator, U10

0x70/ 0x71
EEPROM, U250x50
Address table of the I2C bus slave devices

MIOs

MIO PinConnected toB2BNotes
0...5QSPI Flash, U7-SPI Flash
7...12QSPI Flash, U17-SPI Flash
13...23eMMC, U6
eMMC
24ETH Transceiver, U8-ETH_RST
25USB2.0 Transceiver, U18-OTG_RST
26...33User MIOJM1
34...37N.C-N.C
38...39EEPROM, U25-I2C_SDA/SCL
40...45N.C
N.C
46...51SD CardJM1
52...63USB2.0 Transceiver, U18-
63...77Ethernet Transceiver, U8-
MIOs pins

Test Points

Test PointSignalConnected toNotes
1PS_LP0V85Voltage Regulator, U12
2DDR_2V5Voltage Regulator, U4
3PS_AVCCVoltage Regulator, U9
4DDR_1V2Voltage Regulator, U15
5PS_AVTTVoltage Regulator, U3
6VTTRegulator, U16
7PS_FP0V85Voltage Regulator, U26
8VREFARegulator, U16
10PS_PLLVoltage Regulator, U23
11PL_VCCINTVoltage Regulator, U5
15PL_VCCINT_IOVoltage Regulator, U27
16PL_VCUVoltage Regulator, U24
Test Points Information

On-board Peripherals

On board peripherals

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module.

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
EN1InputPower Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOODOutputPower GoodOnly indirect used for power status, see CPLD description
NOSEQ--No used for Power sequencing, see CPLD description
RESINInputReset

Active low reset, gated to POR_B

JTAGENInputJTAG SelectLow for normal operation, high for CPLD JTAG access
System Controller CPLD special purpose pins

Please check the entire information at TE0820 CPLD.

See also TE0820 System Controller CPLD page.

eMMC Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

DDR4 Memory

The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB-BIRC
  • Supply voltage: 1.2V
  • Speed: 2400 Mbps
  • Temperature: -40 ~ 95 °C

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHY

PinSchematicConnected toNote
MDIP0...3

PHY_MDI0...3

B2B, JM1


MDC

ETH_MDC

MIO76


MDIOETH_MDIOMIO77
S_INS_INB2B, JM3
S_OUTS_OUTB2B, JM3
TXD0..3ETH_TXD0...3MIO65...68
TX_CTRLETH_TXCTLMIO69
TX_CLKETH_TXCKMIO64
RXD0...3ETH_RXD0...3MIO71...74
RX_CTRLETH_RXCTLMIO75
RX_CLKETH_RXCKMIO70
LED1PHY_LED1CPLD, U21
RESETnETH_RSTMIO24
GigaBit Ethernet connection

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

 PHY PinZYNQ PinB2B NameNotes
ULPIMIO52..63-Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK--52.000000 MHz from on-board oscillator (U14).
REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETBMIO25-Active low reset.
CLKOUTMIO52-Connected to 1.8V, selects reference clock operation mode.
DP, DM-OTG_D_P, OTG_D_NUSB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN-VBUS_V_ENExternal USB power switch active high enable signal, routed to JM3 pin 17.
VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID-OTG_IDFor an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.
General overview of the USB PHY signals

EEPROM

There is a 2Kb EEPROM (U25) provided on the module TE0820.

MIO PinSchematicU25 PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL
I2C EEPROM interface MIOs and pins

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.

U25 PinSignalConnected toDirectionNote

IN0..1

CLK_INJM3IN
IN2CLK_25MOscillator, U11IN
SCLI2C_SCLEEPROM,U25INOUT
SDAI2C_SDAEEPROM,U25INOUT
CLK0CLK0JM3OUT
CLK1B505_CLK3FPGA Bank 505IN
CLK2B505_CLK1FPGA Bank 505IN
CLK3CLK3_N
IN
Programmable Clock Generator Inputs and Outputs

Clock Sources

DesignatorDescriptionFrequencyClock Destination
U32MEMS Oscillator33.33 MHz
U11MEMS Oscillator25 MHz
U14MEMS Oscillator52  MHz
Osillators

LEDs

DesignatorColorConnected toActive LevelNote
D1RedDONELow
D2GreenUSR_LEDHigh
D3RedERR_OUTHigh
D4GreenERR_STATUSHigh
On-board LEDs

Power and Power-on Sequence


Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*
3.3VINTBD*
Power Consumption

 * TBD - To Be Determined soon with reference design setup.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Figure 3: TE0820-03 Power Distribution Diagram


See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.

Power-On Sequence

The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:


Figure 4: TE0820-03 Power-on Sequence Diagram


For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out  is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Power Rail Name on B2B ConnectorJM1 PinsJM2 PinsDirectionNotes
VIN

1, 3, 5

2, 4, 6, 8InputSupply voltage from the carrier board
3.3V-10, 12OutputInternal 3.3V voltage level
3.3VIN13, 15-InputSupply voltage from the carrier board
1.8V39-OutputInternal 1.8V voltage level
JTAG VREF-91OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_64-7, 9InputHigh performance I/O bank voltage
VCCO_65-5InputHigh performance I/O bank voltage
VCCO_669, 11-InputHigh performance I/O bank voltage
Module power rails.

Bank Voltages

FPGA BankSchematicVoltageNote
Bank 24 HDVCCO_HD24_24Variable Max voltage 3.3V
Bank 25 HD
Variable Max voltage 3.3V
Bank 26 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 44 HDVCCO_HD24_44VariableMax voltage 3.3V
Bank 64 HPVCCO_64N.CNot Connected
Bank 65 HP

VCCO_65

VariableMax voltage 1.8V
Bank 66 HPVCCO_661.8V
Bank 500 PSMIOVCCO_PSIO0_5001.8V

Bank 501 PSMIO

VCCO_PSIO1_501

3.3V


Bank 502 PSMIOVCCO_PSIO2_5021.8V
Bank 503 PSCONFIGVCCO_PSIO3_5031.8V
Bank 504 PSDDRDDR_1V21.2V
Zynq SoC bank voltages.

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report 07 04, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report 07 04, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report 07 04, 2016 by Thorsten Trenz




Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet
PS absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsNotes
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range
Recommended operating conditions.

Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm

  • PCB thickness: 1.6 mm

  • Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0820 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

DateRevisionChangesDocumentation Link
2020-08-1404
  • Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips
  • Added R93, changed value C62, change obsolete U28
  • Added R89 (10R)
  • Added additional caps 4.7uF to PS_AVTT/PS_AVCC (Xilinx doc UG583)
  • Changed R51 20k ->10K (PS_AVCC = 0.85V, Xilinx doc DS925 v1.17)
  • Fixed DDR4 connection (Alert)
  • Added 3.3V signal to CPLD
  • Added testpoints
  • LIB components update
PCN-20200616TE0820-4
2019-01-0203
  • Fixed VCU connection: add additional DCDC (0.9V)
  • LIB components update
  • Change package 1K resistors (0402 -> 0201)
  • Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT)
  • Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit)
  • Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85)
  • Changed DCDC (U5) 6A (optional 4A)
PCN-20190110TE0820-03
2017-08-1702
  • Added MAC EEPROM (slave address)
  • LIB components update
  • Fixed SD Card connection
  • Fixed sense connection from DCDC
  • Made correct power connection for VCU (removed DCDC, added resistors and caps like as Xilinx recommended)
  • Added resistors for variants (ZU+ with/without VCU)
  • Added termination resistors (240R) to VRP pins fro all HP-banks
PCN-20171117TE0820-02
2016-12-2301Prototype only-TE0820-01
Hardware Revision History


Figure 6: Module hardware revision number

Document Change History

DateRevisionContributorDescription

  • bugfix boot mode
2021-07-05v.97John Hartfiel
  • published
  • style changes
2020-09-18v.95Pedram Babakhani
  • Update to REV04
  • Update the TRM format
  • Technical Information update
2020-03-16v.87John Hartfiel
  • Corrected PLL section
  • Corrected Designators USB, ETH PHY, CLK section
2020-02-03v.85Martin Rohrmüller
  • Corrected #MIOs for QSPI and USB in block diagram
2019-11-28v.81Martin Rohrmüller
  • typo and designator in section USB interface corrected
2019-10-30v.80John Hartfiel
  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version

--

all

  • --
Document change history.


Table 21: Document change history

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