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Overview

The Trenz Electronic TE0820 is an industrial-grade 4 x 5 cm MPSoC SoM (System on Module) module integrating a Xilinx Zynq UltraScale+ with up to 4 GByte 32-Bit DDR4 SDRAM, max. 128 MByte SPI Boot Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Key Features

  • Xilinx Zynq UltraScale+ MPSoC (XCZU2CG / XCZU2EG, XCZU3CG / XCZU3EG or XCZU4CG / XCZU4EV)
    • Quad-core or dual-core Cortex-A53 64-bit ARM v8 application processing unit (APU) (depends on assembly variant CG,EG,EV)
    • Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)
    • Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:

      • PCI Express® interface version 2.1 compliant
      • SATA 3.1 specification compliant interface
      • DisplayPort source-only interface with video resolution up to 4k x 2k

      • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
      • 1 GB/s serial GMII interface
    • 132 x HP PL I/Os (3 banks)
    • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
    • 4 x serial PS GTR transceivers
  • 2 GByte DDR4 SDRAM, 32bit databus-width
  • 128 MByte QSPI boot Flash in dual parallel mode
  • 8 GByte eMMC
  • Programmable quad PLL clock generator PLL for PS GTR clocks (optional external reference)
  • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
  • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
  • All power supplies on board
  • Size: 50 x 40 mm


Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0820-03 block diagram

Main Components

Figure 2: TE0820-03 main components


  1. Xilinx Zynq UltraScale+ MPSoC, U1
  2. 1.8V, 512 Mbit QSPI flash memory, U7
  3. 1.8V, 512 Mbit QSPI flash memory, U17
  4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
  5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
  6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
  8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
  11. 8 GByte eMMC memory, U6
  12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
  13. I2C programmable, any  frequency , any output  quad clock generator, U10
  14. Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
  15. LED D1(Red) Done Pin
  16. LED D2 (Green) CPLD Status, User LED
  17. LED D3 (Red) PS Error
  18. LED D4 (Green) PS Error Status

Initial Delivery State

 Storage Device Name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Not programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5338 OTP NVMNot programmed-
CPLD (LCMXO2-256HC)SC0820-02 QSPI FirmwareSee Boot Process section.

Table 1: Initial delivery state of programmable devices on the module

Boot Process

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

B2B JM1 MODE PinDefault CPLD FirmwareQSPI Firmware VersionSD Card Firmware Version
LowSDJTAGBoot from SD Card
HighFlashBoot from FlashJTAG

Table 2: Boot mode pin description

For more information refer to the TE0820 CPLD - BootMode section. 

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

BankType

B2B Connector

I/O Signal Count

VoltageNotes

64

HP

JM2

48

User

Max voltage 1.8V

64

HP

JM2

2

User

Max voltage 1.8V
65

HP

JM2

18

User

Max voltage 1.8V

65

HP

JM3

16

User

Max voltage 1.8V

66

HP

JM1

48

User

Max voltage 1.8V
500MIOJM181.8V-

501

MIO

JM1

6

3.3V

-

505

GTR

JM3

4 lanes

-

-

505

GTR CLK

JM3

1 differential input

-

-

Table 3: General overview of board to board I/O signals

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
0505GTR
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27
  • PS_MGTRRXP0_505, F27
  • PS_MGTRRXN0_505, F28
  • PS_MGTRTXP0_505, E25
  • PS_MGTRTXN0_505, E26
1505GTR
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21
  • PS_MGTRRXP1_505, D27
  • PS_MGTRRXN1_505, D28
  • PS_MGTRTXP1_505, D23
  • PS_MGTRTXN1_505, D24
2505GTR
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • PS_MGTRRXP0_505, B27
  • PS_MGTRRXN0_505, B28
  • PS_MGTRTXP0_505, C25
  • PS_MGTRTXN0_505, C26
3505GTR
  • B505_RX3_P
  • B505_RX3_N
  • B505_TX3_P
  • B505_TX3_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • PS_MGTRRXP1_505, A25
  • PS_MGTRRXN1_505, A26
  • PS_MGTRTXP1_505, B23
  • PS_MGTRTXN1_505, B24

Table 4: MGT lanes


There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Clock signalBankSourceFPGA PinNotes
B505_CLK0_P505B2B, JM3-31PS_MGTREFCLK0P_505, F23Supplied by the carrier board
B505_CLK0_N505B2B, JM3-33PS_MGTREFCLK0N_505, F24Supplied by the carrier board
B505_CLK1_P505U10, CLK2APS_MGTREFCLK1P_505, E21On-board Si5338A
B505_CLK1_N505U10, CLK2BPS_MGTREFCLK1N_505, E22On-board Si5338A
B505_CLK2_P505N/APS_MGTREFCLK2P_505, C21Not connected
B505_CLK2_N505N/APS_MGTREFCLK2N_505, C22Not connected
B505_CLK3_P505U10, CLK1APS_MGTREFCLK3P_505, A21On-board Si5338A
B505_CLK3_N505U10, CLK1BPS_MGTREFCLK3N_505, A22On-board Si5338A

Table 5: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

JTAG Signal

B2B Connector Pin

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99 

Table 6: JTAG interface signals

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
EN1InputPower Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOODOutputPower GoodOnly indirect used for power status, see CPLD description
NOSEQ--No used for Power sequencing, see CPLD description
RESINInputReset

Active low reset, gated to POR_B

JTAGENInputJTAG SelectLow for normal operation, high for CPLD JTAG access

Table 7: System Controller CPLD special purpose pins.

See also

Default PS MIO Mapping

PS MIOFunctionB2B PinConnected toPS MIOFunctionB2B PinConnected to
0SPI0-U7-B2, CLK40..45--Not connected
1SPI0-U7-D2, DO/IO1
46SDJM1-17B2B, SD_DAT3
2SPI0-U7-C4, WP/IO2
47SD

JM1-19

B2B, SD_DAT2
3SPI0-U7-D4, HOLD/IO348SD

JM1-21

B2B, SD_DAT1
4SPI0-U7-D3, DI/IO0 49SDJM1-23B2B, SD_DAT0
5SPI0- U7-C2, CS50SDJM1-25B2B, SD_CMD
6N/A-Not connected51SDJM1-27B2B, SD_CLK
7SPI1-U17-C2, CS52USB_PHY-U18-31, OTG-DIR
8SPI1-U17-D3, DI/IO053USB_PHY-U18-31, OTG-DIR
9SPI1-U17-D2, DO/IO154USB_PHY-U18-5, OTG-DATA2
10SPI1-U17-C4, WP/IO255USB_PHY-U18-2, OTG-NXT
11SPI1-U17-D4, HOLD/IO356USB_PHY-U18-3, OTG-DATA0
12SPI1-U17-B2, CLK57USB_PHY-U18-4, OTG-DATA1
13..20eMMC-U6, MMC-D0..D758USB_PHY-U18-29, OTG-STP
21eMMC-U6, MMC-CMD59USB_PHY-U18-6, OTG-DATA3
22eMMC-U6, MMC-CLKR60USB_PHY-U18-7, OTG-DATA4
23eMMC-U6, MMC-RST61USB_PHY-U18-9, OTG-DATA5
24ETH-U8, ETH-RST62USB_PHY-U18-10, OTG-DATA6
25USB_PHY-U18, OTG-RST

63

USB_PHY-U18-13, OTG-DATA7
26MIOJM1-95B2B, as PJTAG MIO possible64ETH-U8-53, ETH-TXCK
27MIOJM1-93B2B, as PJTAG MIO possible65..66ETH-U8-50..51, ETH-TXD0..1
28MIOJM1-99B2B, as PJTAG MIO possible67..68ETH-U8-54..55, ETH-TXD2..3
29MIOJM1-97B2B, as PJTAG MIO possible69ETH-U8-56, ETH-TXCTL
30MIOJM1-92B2B (UART RX)70ETH-U8-46, ETH-RXCK
31MIOJM1-85B2B (UART TX)71..72ETH-U8-44..45, ETH-RXD0..1
32MIOJM1-91B2B73..74ETH-U8-47..48, ETH-RXD2..3
33MIOJM1-87B2B75ETH-U8-43, ETH-RXCTL
34..37--Not connected76ETH-U8-7, ETH-MDC
38I2C-U10-12, SCL77ETH-U8-8, ETH-MDIO
39I2C-U10-19, SDA----

Table 8: TE0820-03 PS MIO mapping

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

Ethernet PHY connection

PHY PinZYNQ PSZYNQ PLNotes
MDC/MDIOMIO76, MIO77--
LED0-K8Can be routed via PL to any free PL I/O pin in B2B connector.
LED1--CPLD pin 17.
LED2--Not connected.
CONFIG--Wired to the 1.8V.
RESETnMIO24--
RGMIIMIO64..MIO75--
SGMII--Routed to the B2B connector JM3.

Table 9: General overview of the Gigabit Ethernet PHY signals

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 25.000000 MHz oscillator (U15).

USB PHY connection

 PHY PinZYNQ PinB2B NameNotes
ULPIMIO52..63-Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK--52.000000 MHz from on-board oscillator (U14).
REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETBMIO25-Active low reset.
CLKOUTMIO52-Connected to 1.8V, selects reference clock operation mode.
DP, DM-OTG_D_P, OTG_D_NUSB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN-VBUS_V_ENExternal USB power switch active high enable signal, routed to JM3 pin 17.
VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID-OTG_IDFor an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

Table 10: General overview of the USB PHY signals.

I2C Interface

On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:

I2C DeviceI2C AddressNotes

Si5338A PLL

0x70-
EEPROM0x50-

Table 11: Address table of the I2C bus slave devices.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0820 System Controller CPLD page.

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

DDR4 Memory

By default TE0820-03 module has two 16-bit wide Samsung K4A8G165WB DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U21).

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U25) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x50.

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.

SignalFrequencyNotes
IN1/IN2user

External clock signal supply from B2B connector JM3, pins JM3-32/JM3-34

IN3

25.000000 MHz

Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U11)

IN4-LSB of the default I2C address, wired to ground mean address is 0x70

IN5

-

Not connected

IN6

-

Wired to ground
CLK0 A/B

-

Bank 65 clock input, pins K9 and J9

CLK1 A/B

-

MGT reference clock 3 to FPGA Bank 505 PS GTR

CLK2 A/B

-

MGT reference clock 1 to FPGA Bank 505 PS GTR

CLK3 A/B-Not connected

Table 12: General overview of the on-board quad clock generator I/O signals

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008BI oscillator, U21PS_CLK33.333333 MHzZynq MPSoC U1,pin R16
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U10, pin 3, and Ethernet  PHY U8, pin 34

Table 13: Reference clock signals

On-board LEDs

LEDColorConnected toDescription and Notes
D1RedPS Config bank 503Reflects inverted DONE signal when FPGA configuration is completed
D2GreenSystem Controller CPLD, bank 3Exact function is defined by SC CPLD firmware
D3RedPS Config bank 503Reflects Zynq MPSoC control signal 'ERR_OUT'
D4GreenPS Config bank 503Reflects Zynq MPSoC control signal 'ERR_STATUS'

Table 14: On-board LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Power InputTypical Current
VINTBD*
3.3VINTBD*

Table 15: Power consumption


 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

Figure 3: TE0820-03 Power Distribution Diagram


See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Figure 4: TE0820-03 Power-on Sequence Diagram


For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Power Rail Name on B2B ConnectorJM1 PinsJM2 PinsDirectionNotes
VIN

1, 3, 5

2, 4, 6, 8InputSupply voltage from the carrier board
3.3V-10, 12OutputInternal 3.3V voltage level
3.3VIN13, 15-InputSupply voltage from the carrier board
1.8V39-OutputInternal 1.8V voltage level
JTAG VREF-91OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_64-7, 9InputHigh performance I/O bank voltage
VCCO_65-5InputHigh performance I/O bank voltage
VCCO_669, 11-InputHigh performance I/O bank voltage

Table 16: TE0820-03 power rails

Bank Voltages

BankName on SchematicVoltageRange
64 HPVCCO_64UserHP: 1.0V to 1.8V
65 HPVCCO_65UserHP: 1.0V to 1.8V
66 HPVCCO_66UserHP: 1.0V to 1.8V
500 PSMIOVCCO_PSIO0_5001.8V -
501 PSMIOVCCO_PSIO1_5013.3V -
502 PSMIOVCCO_PSIO2_5021.8V-
503 PSCONFIGVCCO_PSIO3_5031.8V-
504 PSDDRVCCO_PSDDR_5041.2V-

Table 17: TE0820-03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report 07 04, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report 07 04, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report 07 04, 2016 by Thorsten Trenz



Variants Currently In Production

Trenz shop TE0820 overview page
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Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet

Table 18: Module absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsNotes
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range

Table 19: Recommended operating conditions


Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

See Xilinx datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips.

Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm

  • PCB thickness: 1.6 mm

  • Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.


   

Figure 5: Module physical dimensions drawing

Revision History

Hardware Revision History

DateRevision

Notes

PCN LinkDocumentation Link
-03current available module revision-TE0820-03
2017-08-1702--PCN-20171117TE0820-02
2016-12-2301Prototype only-TE0820-01

Table 20: Hardware revision history table


Figure 6: Module hardware revision number

Document Change History


Date

Revision

Contributors

Description

  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version
--all
  • ---

Table 21: Document change history

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