Page History
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| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | 3.3 | 3.6 | V | EN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
| DCDCIN | 3.3 | 3.6 | V | TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG |
| LP_DCDC | 3.3 | 3.6 | V | TPS3106K33DBVR data sheet |
| GT_DCDC | 23.53 | 3.6 | V | TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
| PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
| VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, see schematic for connected VCCs |
| Voltage on input pins (MR) of TPS3106K33DBVR Voltage Monitor, U41 | 0 | VDD | V | TPS3106 data sheet, VDD = LP_DCDC |
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