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The Trenz Electronic TE0803 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width data bus connection, max. 512 MByte SPI Boot Flash memory for configuration and operation, up to 8 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price

Key Features

  • Xilinx Zynq UltraScale+ MPSoC 784 pin package (options: ZU2CG, ZU2EG, ZU3CG, ZU3EG, ZU4CG, ZU4EV)
  • Memory
    - 64-Bit DDR4, 8 GByte maximum
    - Dual SPI boot Flash in parallel, 128 MByte maximum
  • User I/O
    - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
    - Serial transceiver: 4 x GTR (+ 4 x GTH transceiver with ZU4CG or ZU4EV MPSoC)
    - Transceiver clocks inputs and outputs
    - PLL clock generator inputs and outputs
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin
  • Si5338A - 4 output PLL
  • All power supplies on board, single 3.3V power source required
    - LP, FP, PL separately controlled power domains
  • Support for all boot modes (except NAND) and scenarios
  • Support for any combination of PS connected peripherals

Block Diagram

Figure 1: TE0803-01 Block Diagram

Main Components


Figure 2: TE0803-01 MPSoC module

  1. Xilinx ZYNQ UltraScale+ MPSoC, U1
  2. 2-Input AND Gate, U39
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. PowerSoC DC-DC converter, U4 (either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
  9. 1.5A LDO DC-DC converter, U10
  10. 1.5A LDO DC-DC converter, U8
  11. Voltage monitor circuit, U41
  12. 0.35A LDO DC-DC converter, U26
  13. 0.35A LDO DC-DC converter, U27
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  18. 4-channel programmable PLL clock generator, U5
  19. Low-power programmable oscillator @ 25.000000 MHz, U5
  20. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  21. 256 Mbit serial NOR Flash memory, U7
  22. 256 Mbit serial NOR Flash memory, U17

Initial Delivery State

 Storage device name



User configuration EEPROMs with MAC address (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)

Not programmed

available since PCB REV02

SPI Flash main array

Not programmed


eFUSE Security

Not programmed

Si5338A programmable PLL NVM OTPNot programmedOnly volatile memory is programmable of field. NVM can't be program on field. Custom assembly variant with preprogrammed NVM is possible on request

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0803 MPSoC SoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltraScale+ MPSoC like I/O-banks, interfaces and Gigabit transceivers
or to the on-board peripherals.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

BankTypeB2B ConnectorSchematic Names / Connector PinsI/O Signal CountLVDS Pairs CountVCCO Bank VoltageNotes



B25_L1_P ... B25_L12_P
B25_L1_N ... B25_L12_N

24 I/O's12

pins J3-15, J3-16

VCCO max. 3.3V
usable as single-ended I/O's



B26_L1_P ... B26_L12_P
B26_L1_N ... B26_L12_N

24 I/O's12

pins J3-43, J3-44

VCCO max. 3.3V
usable as single-ended I/O's


B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

B64_T0 ... B64_T3

52 I/O's24

pins J4-58, J4-106

VCCO max. 1.8V
usable as single-ended I/O's


B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

B65_T0 ... B65_T3

52 I/O's24

pins J4-69, J4-105

VCCO max. 1.8V
usable as single-ended I/O's


B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N

B66_T0 ... B66_T3

52 I/O's24

pins J1-90, J1-120

VCCO max. 1.8V
usable as single-ended I/O's

500MIOJ3MIO13 ... MIO2513 I/O's-PS_1V8user configurable I/O's on B2B
501MIOJ3MIO26 ... MIO5126 I/O's-PS_1V8user configurable I/O's on B2B
502MIOJ3MIO52 ... MIO7726 I/O's-PS_1V8user configurable I/O's on B2B

Table 2: B2B connector pin-outs of available PL and PS banks of the TE0803-01 SoM

              1) Bank 25 at XCZU2 / XCZU3, else Bank 45 at XCZU4 / XCZU5

              2) Bank 26 at XCZU2 / XCZU3, else Bank 46 at XCZU4 / XCZU5

All MIO banks are powered from on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the B2B pin-out, please refer to the Pin-out table. 

The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT lanes are available on the B2B connectors:

BankTypeB2B ConnectorCount of MGT LanesSchematic Names / Connector PinsMGT Bank's Reference Clock Inputs



4 GTH lanes

(4 RX / 4TX)

B224_RX3_P, B224_RX3_N, pins J1-51, J1-53
B224_TX3_P, B224_TX3_N, pins J1-50, J1-52

B224_RX2_P, B224_RX2_N, pins J1-57, J1-59
B224_TX2_P, B224_TX2_N, pins J1-56, J1-58

B224_RX1_P, B224_RX1_N, pins J1-63, J1-65
B224_TX1_P, B224_TX1_N, pins J1-62, J1-64

B224_RX0_P, B224_RX0_N, pins J1-69, J1-71
B224_TX0_P, B224_TX0_N, pins J1-68, J1-70

1 reference clock signal (B224_CLK0) from B2B connector
J3 (pins J3-59/J3-61) to bank's pins Y6/Y5

1 reference clock signal (B224_CLK1) from programmable
PLL clock generator U5 to bank's pins V6/V5


4 GTR lanes

(4 RX / 4TX)

B505_RX3_P, B505_RX3_N, pins J2-54, J2-52
B505_TX3_P, B505_TX3_N, pins J2-51, J2-49

B505_RX2_P, B505_RX2_N, pins J2-60, J2-58
B505_TX2_P, B505_TX2_N, pins J2-57, J2-55

B505_RX1_P, B505_RX1_N, pins J2-66, J2-64
B505_TX1_P, B505_TX1_N, pins J2-63, J2-61

B505_RX0_P, B505_RX0_N, pins J2-72, J2-70
B505_TX0_P, B505_TX0_N, pins J2-69, J2-67

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-16/J2-18, J2-10/J2-12) to bank's pins F23/F24, E21/E22

2 reference clock signals (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins C21/C22, A21/A22

Table 3: B2B connector pin-outs of available MGT lanes of the MPSoC

              1) Bank 224 only available at XCZU4 / XCZU5 MPSoC.

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.

JTAG SignalB2B Connector Pin

Table 4: B2B connector pin-out of JTAG interface

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed
PROG_BJ2-100PL configuration reset signal
INIT_BJ2-98PS is initialized after a power-on reset
SRST_BJ2-96System reset
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103

4-bit boot mode pins

For further information about the boot-modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM
section 'Boot and Configuration'.


ERR_OUT signal is asserted for accidental loss of
power, an error, or an exception in the MPSoC's Platform Management Unit (PMU)

ERR_STATUS indicates a secure lock-down state

PUDC_BJ2-127Pull-up during configuration (pulled-up to 'PL_1V8')

Table 5: B2B connector pin-out of MPSoC's PS configuration bank

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

SignalB2B Connector PinFunction
V_P, V_NJ2-113, J2-115System Monitor
DX_P, DX_NJ2-119, J2-121Temperature-sensing diode pins

Table 6: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0..MIO5 and MIO7..MIO12.

MIOU7 PinPin Name
MIOU17 PinPin Name

Table 7: MIO pin assignment of the Quad SPI Flash memory ICs

Boot Process

The boot source of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:

Boot Mode PinB2B Pin

Table 8: Boot mode pins on B2B connector J2

Following boot modes are possible on the TE0803 UltraScale+ MPSoC module by generating the corresponding 4-bit code with pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):

Boot ModeMode Pins [3:0]MIO LocationDescription
JTAG0x0JTAGDedicated PS interface.

Configured on module with dual QSPI Flash Memory.

32-bit addressing.
Supports single and dual parallel configurations.
Stack and dual stack is not supported.

SD00x3MIO[25:13]Supports SD 2.0.
SD10x5MIO[51:38]Supports SD 2.0.
eMMC_180x6MIO[22:13]Supports eMMC 4.5 at 1.8V.
USB 00x7MIO[52:63]Supports USB 2.0 and USB 3.0.
PJTAG_00x8MIO[29:26]PS JTAG connection 0 option.

Supports SD 3.0 with a required
SD 3.0 compliant level shifter.

Table 9: Selectable boot modes by dedicated boot mode pins

For functional details see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

On-board Peripherals


The TE0803 SoM can be configured with max. 512 MByte Flash memory for configuration and operation. Flash size and type depends on assembly version.

SPI FlashU7QSPI0MIO0 ... MIO5Dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration
SPI FlashU17QSPI0MIO7 ... MIO12As above

Table 10: Peripherals connected to the PS MIO pins


The TE0803-01 SoM is equipped with with four DDR4-2400 SDRAM chips  with up to 8 GByte of memory. The SDRAM chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) via 64-bit wide  data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information, if the specific Zynq UltraScale+ MPSoC chip on module supports the maximum data transmission rate of 2400 MByte/s.

Configuration EEPROM

The TE0803 (PCB REV02 or newer) contains EEPROMs for general user purposes and mac address. The EEPROMs are provided by Microchip and all have I²C interfaces:

EEPROM ModellSchematic DesignatorMemory DensityPurpose
24AA025E48T-I/OTU412 Kbituser

Table 21:  On-board configuration EEPROMs overview

Programmable PLL Clock Generator

Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and outputs:

InputConnected toFrequencyNotes
IN1 / IN2B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN3On-board Oscillator (U6)25.000000 MHz-
OutputConnected toFrequencyNotes
CLK0 A/BB2B Connector pins J2-1, J2-3 (differential pair)UserDefault off
CLK1 A/BB224 CLK1 (only available at MPSoC with ZU4 and higher )UserDefault off
CLK2 A/BB505 CLK3UserDefault off
CLK3 A/BB505 CLK2UserDefault off

Table 11: Programmable PLL clock generator input/output

The Si5338A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5338A data sheet.

SignalB2B Connector pinFunction
PLL_SCL / PLL_SDAJ2-90 / J2-92

I²C interface, external pull-ups needed for SCL/SDA line.

I²C address in current configuration: 1110000b

Table 12: B2B connector pin-out of Si5338A control interface

Si5338A  NVM  is not programmed by default at delivery. It is customers responsibility to either configure Si5338A volatile memory during FSBL or then use Silicon Labs programmer.  Custom assembly variant with preprogrammed NVM is possible on request.

Refer to Si5338A datasheet for more information.


The TE0803-01 SoM is equipped with two on-board oscillators to provide the Zynq MPSoC's PS configuration bank 503 with reference clock signals.

ClockFrequencyBank 503 PinConnected to
PS_CLK33.333333 MHzR16MEMS oscillator, U32
PS_PAD (RTC)32.768 kHzN17/N18Quartz crystal, Y2

Table 13: Reference clock-signals to PS configuration bank 503

On-board LEDs

LED ColorConnected toDescription and Notes
D1RedDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

Table 14: LED's description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current

Table 15: Maximum current of power supplies. *To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0803 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular external DC-DC converters.

The Processing System contains three Power Domains:

  • Battery Power Domain (BBRAM and RTC)
  • Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
  • Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0803 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

  • Full-Power Domain, supplied by power rail 'DCDCIN'
  • Low-Power Domain, supplied by power rail 'LP_DCDC'
  • Programmable Logic, supplied by power rail 'PL_DCIN'
  • Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signals. The power rail 'GT_DCDC' is only necessary for variants of the TE0803 module with the Xilinx Zynq UltraScale+ ZU4CG or ZU4EV MPSoC to generate the voltages for the available Xilinx GTH unit.

Power Distribution Dependencies

The power rails 'DCDCIN', 'LP_DCDC', 'PL_DCIN', 'PS_BATT' have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered up, with 3.3V power sources, also shared, if Power Domain control is not required.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Figure 3: Power Distribution Diagram (For U4 either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Power-On Sequence Diagram

The TE0803 SoM meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0803 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

  1. Low-Power Domain (LPD)
  2. Programmable Logic (PL) and Full-Power Domain (FPD)
  3. PS GTR transceiver and DDR memory (additionally GTH transceiver at modules with ZU5EV MPSoC)

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram clarifies the sequence of enabling the three power instances utilizing the DC-DC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

Figure 4: Power-On Sequence Utilizing DC-DC Converter Control Signals

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power Good Signals need external pull-up resistors.

Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101max PL_DCINLeft floating for logic high (drive to GND for logic low)
PG_PLJ2-104External pull-up needed (max. voltage 'GT_DCDC'),
Max. sink current 1 mA

TPS82085SIL /
NC7S08P5X datasheet

EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
Max. sink current 1 mA
TPS74801 datasheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
Max. sink current 1 mA
TPS74401 datasheet

External pull-up needed (max. 5.5V),
Max. sink current 1 mA

TPS82085SIL datasheet

Table 16: Recommended operation conditions of DC-DC converter control signals

To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence.

Core voltages and main supply voltages have to reach stable state and their "Power Good" signals have to be asserted before other voltages like bank I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good" signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0803 SoM.

Voltage Monitor Circuit

The voltages 'LP_DCDC' and 'LP_0V85' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

Figure 5: Voltage monitor circuit

Power Rails

Voltages on B2B
B2B J1 PinB2B J2 PinB2B J3 PinB2B J4 PinInput/
PL_DCINJ1-151, J1-153,J1-155, J1-157, J1-159---Input-
DCDCIN-J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159
LP_DCDC-J2-138, J2-140, J2-142, J2-144--Input-
GT_DCDC--J3-157, J3-158, J3-159, J3-160-Input-
PS_1V8-J2-99J3-147, J3-148-OutputInternal voltage level
1.8V nominal output
PL_1V8J1-91, J1-121---OutputInternal voltage level
1.8V nominal output
DDR_1V2-J2-135--OutputInternal voltage level
1.2V nominal output

Table 17: Power rails of the MPSoC module on accessible connectors

Bank Voltages

BankTypeSchematic Name / B2B Connector PinsVoltageReference Input VoltageVoltage Range
25HDVCCO25, pins J3-15, J3-16User-Max. 3.3V
26HDVCCO26, pins J3-43, J3-44User-Max. 3.3V
64HPVCCO64, J4-58, J4-106UserVREF_64, pin J4-88Max. 1.8V
65HPVCCO65, J4-69, J4-105UserVREF_65, pin J4-15Max. 1.8V
66HPVCCO66, J1-90, J1-120UserVREF_66, pin J1-108Max. 1.8V

Table 18: Range of MPSoC module's bank voltages

B2B connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
  • 4x REF-192552-02 (160-pins)
    • ST5 Mates with SS5

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec Razor Beam LP Socket Strip (SS5) on the top side.

  • 4x REF192552-01 (160-pins)
    • SS5 Mates with ST5
  • Board-to-Board Connector 160-pins, 80 contacts per row
  • Ultrafine .0197" (0.50 mm) pitch
  • Narrow body design saves space on board
  • Lead style -03.5
  • Samtec 28+ Gbps Solution
  • Mates with: ST5
  • Insulator Material: Liquid Crystal Polymer, schwarz
  • Operating Temperature Range: -55°C bis +125°C
  • Lead-Free Solderable: Yes
  • RoHS Konform: Yes

Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm.

Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
27219REF192552-01SS5-80-3.50-L-D-K-TRBaseboard connector3.5mm

Standard connector used on carrier

27018REF-189545-02 SS5-80-3.00-L-D-K-TRBaseboard connector3 mm 

Assembly option on request

27220REF-192552-02 ST5-80-1.50-L-D-P-TRModule connector1.5 mm

Standard connector used on modules

27017REF-189545-01 ST5-80-1.00-L-D-P-TRModule connector1 mm

Assembly option on request


The module can be manufactured using other connectors upon request.

Current Rating

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Connector Speed Ratings

The connector speed rating depends on the stacking height:

Stacking height

Speed rating

4 mm, Single-Ended13GHz/26Gbps
4 mm, Differential13.5GHz/27Gbps
5 mm, Single-Ended13.5GHz/27Gbps
5 mm, Differential20GHz/40 Gbps
Speed rating.

The SS5/ST5 series board-to-board spacing is currently available in 4mm (0.157"), 4.5mm (0.177") and 5mm (0.197") stack heights.

The data in the reports is applicable only to the 4mm and 5mm board-to-board mated connector stack height.

Manufacturer Documentation

  File Modified
PDF File hsc-report-sma_st5-ss5-04mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File hsc-report-sma_st5-ss5-05mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File REF-192552-01.pdf 13 11, 2017 by John Hartfiel
PDF File REF-192552-02.pdf 13 11, 2017 by John Hartfiel
PDF File ss5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-st5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-xx-x.xx-x-d-k-tr-mkt.pdf 13 11, 2017 by John Hartfiel
PDF File st5.pdf 13 11, 2017 by John Hartfiel
PDF File st5-xx-x.xx-x-d-p-tr-mkt.pdf 13 11, 2017 by John Hartfiel

Variants Currently In Production

Trenz shop TE0803 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN-0.34VTPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN-0.34V TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.34VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage
-0.51.2VXilinx DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC
Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41
-0.3VDD + 0.3VTPS3106 data sheet,
"Enable"-signals on TPS82085SIL
-0.37VTPS82085SIL data sheet
Storage temperature (ambient)-40100°CROHM Semiconductor SML-P11 Series data sheet
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN3.33.6VEN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
DCDCIN3.33.6VTPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC3.33.6VTPS3106K33DBVR data sheet
GT_DCDC3.33.6VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT1.21.5VXilinx DS925 data sheet
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCVNC7S08P5X data sheet,
see schematic for connected VCCs
Voltage on input pins (MR) of
TPS3106K33DBVR Voltage Monitor, U41
0VDDVTPS3106 data sheet,
Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers
  • Mating height with standard connectors: 5mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.


Revision History

Hardware Revision History

 DateRevisionNotesLink to PCNDocumentation Link
  • Added support of DDP DDR4
  • Added support of Low power FPGA (-L1/L2).
  • Revised testpoints
  • Revised J1-J4 connectors net label style
TE0803 Product Change NotificationsTE0803-03
  • Added LDO to DDR_PLL
  • All differential pairs length matched with tollerance 0.1mm (excluding package delays)
  • Added MAC EEPROM U28
  • VPS_MGTRAVCC set to 0.85V
  • Added pull-up resistors R68, R69
TE0803 Product Change NotificationsTE0803-02
2016-12-2301First production release-TE0803-01

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Document Change History


  • Added note regarding DCDC U4.


John Hartfiel

  • Add Note to PLL
22-02-08v.46John Hartfiel
  • Correction on Power section
  • Correction GTH Clock connection
2021-05-17v.41John Hartfiel
  • typo correction in DDR section
2021-03-11v.40John Hartfiel
  • typo
  • fixed MGT Lanes RX/TX order
2019-07-15v.36John Hartfiel
  • correction SPLL section
2019-07-02v.35John Hartfiel
  • add eeprom section
  • update PCB Revision section
2019-06-19v.33John Hartfiel
  • update links
  • correction flash section


v.29John Hartfiel
  • power section: add missing PS_1V8 output pin


v.28John Hartfiel
  • typo correction
2017-11-13v.23Ali Naseri
  • updated B2B connector max. current rating per pin



John Hartfiel
  • rework B2B section


John Hartfiel
  • Removed ES1 Note
2017-08-15v.17Vitali Tsiukala
  • Changed Signals Count in the table B2B-connectors



Jan Kumann
  • New smaller images.
  • New QSPI Flash MIO mapping table.
  • Temperature information changes.
  • Few corrections.



Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.


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