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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Table of contents
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Overview
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Zynq Design PS with Linux and two Ethernet PHYs connected over EMIO and PL.
Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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*used as reference |
Design supports following carriers:
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Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
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Additional Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. MIO Bank 501 Power is Carrier depends and set to 3.3V. Please check Settings, if you use a own carrier. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0820 (optional)
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
Expand title boot process 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze,
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0/ETH1 check) cd /etc/init.d/networking restart (Network setting can be reset if it is necessary) ifconfig (It is visible that both ethernet devices eth0 and eth1 have their own IP address.)
System Design - Vivado
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Block Design
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PS Interfaces
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Constrains
Basic module constrains
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# # Common bitgen related settings # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
Design specific constrain
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############# #ETH0/ETH1 ##### #pwr_down set_property PACKAGE_PIN L21 [get_ports {PHY_PD[0]}] set_property PACKAGE_PIN R20 [get_ports {PHY_PD[1]}] #rst_n set_property PACKAGE_PIN M15 [get_ports {PHY_RSTN[0]}] set_property PACKAGE_PIN R16 [get_ports {PHY_RSTN[1]}] #io standard set_property IOSTANDARD LVCMOS33 [get_ports {PHY*}] set_property IOSTANDARD LVCMOS33 [get_ports MDIO_*] set_property IOSTANDARD LVCMOS33 [get_ports {MII_*}] #pullup/down for PHY address 1 set_property PULLUP true [get_ports MII_col] set_property PULLDOWN true [get_ports {MII_rxd[0]}] set_property PULLDOWN true [get_ports {MII_rxd[1]}] set_property PULLDOWN true [get_ports {MII_rxd[2]}] set_property PULLDOWN true [get_ports {MII_rxd[3]}] #pullup/down for PHY address 3 set_property PULLUP true [get_ports MII_1_col] set_property PULLUP true [get_ports {MII_1_rxd[0]}] set_property PULLDOWN true [get_ports {MII_1_rxd[1]}] set_property PULLDOWN true [get_ports {MII_1_rxd[2]}] set_property PULLDOWN true [get_ports {MII_1_rxd[3]}] ############# #ETH0 ##### set_property PACKAGE_PIN M16 [get_ports MDIO_ETHERNET_0_mdio_io] set_property PACKAGE_PIN P16 [get_ports MDIO_ETHERNET_0_mdc] set_property PACKAGE_PIN M22 [get_ports {MII_txd[3]}] set_property PACKAGE_PIN K21 [get_ports {MII_txd[2]}] set_property PACKAGE_PIN M17 [get_ports {MII_txd[1]}] set_property PACKAGE_PIN J22 [get_ports {MII_txd[0]}] set_property PACKAGE_PIN J20 [get_ports {MII_rxd[3]}] set_property PACKAGE_PIN J18 [get_ports {MII_rxd[2]}] set_property PACKAGE_PIN K18 [get_ports {MII_rxd[1]}] set_property PACKAGE_PIN L17 [get_ports {MII_rxd[0]}] set_property PACKAGE_PIN L16 [get_ports MII_col] set_property PACKAGE_PIN N15 [get_ports MII_crs] set_property PACKAGE_PIN L18 [get_ports MII_rx_clk] set_property PACKAGE_PIN P15 [get_ports MII_rx_dv] set_property PACKAGE_PIN P17 [get_ports MII_rx_er] set_property PACKAGE_PIN K19 [get_ports MII_tx_clk] set_property PACKAGE_PIN J21 [get_ports MII_tx_en] ############# #ETH1 ##### set_property PACKAGE_PIN T16 [get_ports MDIO_ETHERNET_1_mdio_io] set_property PACKAGE_PIN T17 [get_ports MDIO_ETHERNET_1_mdc] set_property PACKAGE_PIN R21 [get_ports {MII_1_txd[3]}] set_property PACKAGE_PIN P22 [get_ports {MII_1_txd[2]}] set_property PACKAGE_PIN P21 [get_ports {MII_1_txd[1]}] set_property PACKAGE_PIN N22 [get_ports {MII_1_txd[0]}] set_property PACKAGE_PIN T19 [get_ports {MII_1_rxd[3]}] set_property PACKAGE_PIN T18 [get_ports {MII_1_rxd[2]}] set_property PACKAGE_PIN R19 [get_ports {MII_1_rxd[1]}] set_property PACKAGE_PIN R18 [get_ports {MII_1_rxd[0]}] set_property PACKAGE_PIN P20 [get_ports MII_1_col] set_property PACKAGE_PIN N18 [get_ports MII_1_crs] set_property PACKAGE_PIN M19 [get_ports MII_1_rx_clk] set_property PACKAGE_PIN N17 [get_ports MII_1_rx_dv] set_property PACKAGE_PIN P18 [get_ports MII_1_rx_er] set_property PACKAGE_PIN N19 [get_ports MII_1_tx_clk] set_property PACKAGE_PIN M21 [get_ports MII_1_tx_en] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
zynq_fsbl
TE modified 2020.2 FSBL
General:
- Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- only active FSBL banner independence form debug flags
zynq_fsbl_flash
TE modified 2020.2 FSBL
FSBL(for Vivado/Vitis GUI only) to initialise Zynq for QSPI programming
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0728
Hello TE0728 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- No changes.
U-Boot
Start with petalinux-config -c u-boot
Changes:
- No changes.
Device Tree
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/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* SDIO */ &sdhci0 { disable-wp; }; /* ETH PHY */ &gem0{ status = "okay"; phy-mode = "mii"; phy-handle = <&phy1>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { device_type = "ethernet-phy"; compatible = "ethernet-phy-id2000.5C90"; max-speed = <0x64>; reg = <1>; }; }; }; &gem1{ status = "okay"; phy-mode = "mii"; phy-handle = <&phy3>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy3: phy@3 { device_type = "ethernet-phy"; compatible = "ethernet-phy-id2000.5C90"; max-speed = <0x64>; reg = <3>; }; }; }; /* RTC */ &i2c0 { rtc@56 { // Real Time Clock compatible = "rv3029c2"; reg = <0x56>; }; }; |
FSBL patch
Must be add manually, see template
Kernel
Start with petalinux-config -c kernel
Changes:
- RTC_DRV_RV3029C2=y
- DP83848_PHY=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- I2C-tools=y
- CONFIG_util-linux-mount=y
- CONFIG_util-linux-umount=y
- busybox-httpd = y
- CONFIG_util-linux-umount=y
- CONFIG_util-linux-mount=y
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Legal Notices
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