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Zynq Design PS with Linux and  two Ethernet PHYs connected over EMIO and PL.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2
  • PetaLinux
  • SD
  • 2x ETH (Independent MDIO Interface and DP83848 PHY)
  • I2C
  • RTC
  • Special FSBL for QSPI programming

Revision History

DateVivadoProject BuiltAuthorsDescription
Mohsen Chamanbaz
  • 2020.2 release
John Hartfiel
  • rework board part files
  • rework petalinux device tree, driver
  • small changes on xdc
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
Wrong UBoot ETH PHY AddressPHY Address is not set correctly for UBoot---solved with 2018-12-12 update

Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz"

This can be ignored, ETH works.------
Known Issues



Vitis2020.2needed, Vivado is included into Vitis installation


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0728-03-1Q03_1qREV01, REV02, REV03512MB16MB


*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
TE0790 XMOD Programmer
Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources


<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files

Vivado Project will be generated by TE Scripts
Vitis<project folde>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes<project folder>\misc\sd\Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

MIO Bank 501 Power is Carrier depends and set to 3.3V. Please check Settings, if you use a own carrier.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  8. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  9. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0820 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	              (check I2C 0 Bus)
    dmesg | grep rtc	              (RTC check)
    udhcpc				              (ETH0/ETH1 check)
    cd /etc/init.d/networking restart (Network setting can be reset if it is necessary)
    ifconfig            (It is visible that both ethernet devices eth0 and eth1 have their own IP address.)

System Design - Vivado

Block Design

Block Design

PS Interfaces

PS Interfaces


Basic module constrains

# Common bitgen related settings

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

set_property PACKAGE_PIN L21 [get_ports {PHY_PD[0]}]
set_property PACKAGE_PIN R20 [get_ports {PHY_PD[1]}]
set_property PACKAGE_PIN M15 [get_ports {PHY_RSTN[0]}]
set_property PACKAGE_PIN R16 [get_ports {PHY_RSTN[1]}]
#io standard
set_property IOSTANDARD LVCMOS33 [get_ports {PHY*}]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_*]
set_property IOSTANDARD LVCMOS33 [get_ports {MII_*}]
#pullup/down for PHY address 1
set_property PULLUP   true [get_ports MII_col]
set_property PULLDOWN true [get_ports {MII_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_rxd[3]}]
#pullup/down for PHY address 3
set_property PULLUP true [get_ports MII_1_col]
set_property PULLUP true [get_ports {MII_1_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[3]}]

set_property PACKAGE_PIN M16 [get_ports MDIO_ETHERNET_0_mdio_io]
set_property PACKAGE_PIN P16 [get_ports MDIO_ETHERNET_0_mdc]
set_property PACKAGE_PIN M22 [get_ports {MII_txd[3]}]
set_property PACKAGE_PIN K21 [get_ports {MII_txd[2]}]
set_property PACKAGE_PIN M17 [get_ports {MII_txd[1]}]
set_property PACKAGE_PIN J22 [get_ports {MII_txd[0]}]
set_property PACKAGE_PIN J20 [get_ports {MII_rxd[3]}]
set_property PACKAGE_PIN J18 [get_ports {MII_rxd[2]}]
set_property PACKAGE_PIN K18 [get_ports {MII_rxd[1]}]
set_property PACKAGE_PIN L17 [get_ports {MII_rxd[0]}]
set_property PACKAGE_PIN L16 [get_ports MII_col]
set_property PACKAGE_PIN N15 [get_ports MII_crs]
set_property PACKAGE_PIN L18 [get_ports MII_rx_clk]
set_property PACKAGE_PIN P15 [get_ports MII_rx_dv]
set_property PACKAGE_PIN P17 [get_ports MII_rx_er]
set_property PACKAGE_PIN K19 [get_ports MII_tx_clk]
set_property PACKAGE_PIN J21 [get_ports MII_tx_en]

set_property PACKAGE_PIN T16 [get_ports MDIO_ETHERNET_1_mdio_io]
set_property PACKAGE_PIN T17 [get_ports MDIO_ETHERNET_1_mdc]
set_property PACKAGE_PIN R21 [get_ports {MII_1_txd[3]}]
set_property PACKAGE_PIN P22 [get_ports {MII_1_txd[2]}]
set_property PACKAGE_PIN P21 [get_ports {MII_1_txd[1]}]
set_property PACKAGE_PIN N22 [get_ports {MII_1_txd[0]}]
set_property PACKAGE_PIN T19 [get_ports {MII_1_rxd[3]}]
set_property PACKAGE_PIN T18 [get_ports {MII_1_rxd[2]}]
set_property PACKAGE_PIN R19 [get_ports {MII_1_rxd[1]}]
set_property PACKAGE_PIN R18 [get_ports {MII_1_rxd[0]}]
set_property PACKAGE_PIN P20 [get_ports MII_1_col]
set_property PACKAGE_PIN N18 [get_ports MII_1_crs]
set_property PACKAGE_PIN M19 [get_ports MII_1_rx_clk]
set_property PACKAGE_PIN N17 [get_ports MII_1_rx_dv]
set_property PACKAGE_PIN P18 [get_ports MII_1_rx_er]
set_property PACKAGE_PIN N19 [get_ports MII_1_tx_clk]
set_property PACKAGE_PIN M21 [get_ports MII_1_tx_en]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


TE modified 2020.2 FSBL


  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • only active FSBL banner independence form debug flags


TE modified 2020.2 FSBL

FSBL(for Vivado/Vitis GUI only) to initialise Zynq for QSPI programming


  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello TE0728 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description


  • No changes.


Start with petalinux-config -c u-boot


  • No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

/* SDIO */
&sdhci0 {

/* ETH PHY */
    status = "okay";
    phy-mode = "mii";
    phy-handle = <&phy1>;
    xlnx,has-mdio = <0x1>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy1: phy@1 {
            device_type = "ethernet-phy";
            compatible = "ethernet-phy-id2000.5C90";
        max-speed = <0x64>;
            reg = <1>;
    status = "okay";
    phy-mode = "mii";
    phy-handle = <&phy3>;
    xlnx,has-mdio = <0x1>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy3: phy@3 {
            device_type = "ethernet-phy";
        compatible = "ethernet-phy-id2000.5C90";
        max-speed = <0x64>;
            reg = <3>;
/* RTC */
&i2c0 {
    rtc@56 {        // Real Time Clock
       compatible = "rv3029c2";
       reg = <0x56>;

FSBL patch

Must be add manually, see template


Start with petalinux-config -c kernel


  • RTC_DRV_RV3029C2=y
  • DP83848_PHY=y


Start with petalinux-config -c rootfs


  • I2C-tools=y
  • CONFIG_util-linux-mount=y
  • CONFIG_util-linux-umount=y
  • busybox-httpd = y
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y


See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"


Script App to load from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files


Webserver application suitable for Zynq access. Need busybox-httpd

See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • style changes Revision table
  • remove CLBPro from source list
2021-11-03v.14Mohsen Chamanbaz
  • Release 2020.2
2018-12-12v.13John Hartfiel
  • Release 2018.2
  • Design and Documentation is changed


v.10John Hartfiel
  • Release 2017.2

  • Initial release

Document change history.

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