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^*used as reference

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0807 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

• TE0807 "Test Board" Reference Design

Design Flow

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
3. Press 0 and enter to start "Module Selection Guide"
4. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
5. Create Project (follow instruction Createproject and follow instructions of the product selection guide), settings file will be configured automatically during this process.
   (

   • optional for manual changes

   )

   • : Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see

   TE

   • also Vivado Board Part

   Files

   • Flow Important: Use Board Part Files, which did not

   ends

   • end with *_

   tebf0808

   • tebf0808

     
     

6. Create hardware description file (.xsa file) and

   Create XAS and

   export to prebuilt folder

   
   Run on Vivado TCL:

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

7. Generate Programming Files with Vitis

   
   Run on Vivado TCL: TE::sw_run_vitis -all
   Note: Scripts generate

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")

   (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
   Note: 

   TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   
   

   Note
   TCL scripts generate also platform project, this must be done

   manuelly

   manually in case GUI is used. See Vitis

   
   

Launch

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Note: Programming and Startup procedure

Programming

Xilinx documentation for programming and debugging: Vivado/SDKVitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select

      Create

      create and open delivery binary folder

      Info
      Note: Folder

      (

      "<project

      foler>/

      folder>\_binaries_

      <Artikel

      <Article Name>

      )

      " with subfolder

      (

      "boot_<app name>

      )

      " for different applications will be generated

      
      

QSPI-Boot mode

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Type

   Code Block
   language bash theme Midnight title run on Vivado TCL

   Console:

   (Script programs BOOT.bin on QSPI flash)

   TE::pr_program_flash

   _binfile

   -swapp hello_te0807

   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

SD-Boot mode

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with Vitis Debugger into device.

Usage

QSPI Boot:

1. Prepare HW like described on section 71631609 Programming
2. Connect UART USB (most cases same as JTAG)

3. Select QSPI

   Card

   as Boot Mode

   Info
   Note: See TRM of the Carrier, which is used.

   
   

4. Power On

   PCB
   Note:

   PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM

   loads PMU Firmware and 

   FSBL from QSPI into OCM, 2. FSBL

   loads Application

   init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR

   
   

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title-alignment centerFigure_BD title Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design

- Vitis

Vitis

Application

zynqmp_fsbl

TE modified 20202021.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files:   te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 20202021.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0807

Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

output.

Additional Software

No additional software is needed.

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