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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2
  • QSPI
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
John Hartfiel
  • 2020.2 update
John Hartfiel
  • new assembly variants
John Hartfiel
  • script update
John Hartfiel
  • 2019.2 update
  • Vitis support
John Hartfiel
  • custom FSBL
  • Note: Prebuilt for ES2 version not included
John Hartfiel
  • new assembly variant
John Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
John Hartfiel
  • rework Board Part Files

John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------
Known Issues



Vitis2020.2needed, Vivado is included into Vitis installation


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   es2_2gb      REV01    2GB      64GB       NA         NA     Not longer supported by vivado
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      64GB       NA         NA     NA                               
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      64GB       NA         NA     with heat sink                 
TE0807-02-4BE21-A   4eg_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DE21-A   7ev_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI21-C   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     without encryption             
TE0807-02-7DI21-A   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-4AI21-X   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     U41 replaced with diode        
TE0807-02-4BE21-AK  4eg_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-7DI21-AK   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-5DI21-A   5ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7NE21-A   7ev_3e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-03-5DI21-A   5ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7NE21-A   7ev_3e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-4AI21-X   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     U41 replaced with diode        
TE0807-03-4AI21-A   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-4AI21-C   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
TE0807-03-4BE21-A   4eg_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-5AI21-A   5cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7AI21-A   7cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DE21-A   7ev_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DE21-AK  7ev_1e_4gb   REV03    4GB      128MB      NA         NA     with heat sink                 
TE0807-03-7DI21-A   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DI21-C   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
TE0807-03-7DI24-A   7ev_1i_4gb   REV03    4GB      512MB      NA         NA     NA                               
Hardware Modules

Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Carrier ModelNotes
Custom PCB use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808Used as reference carrier.
TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
Design sources

Additional Sources

Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/ and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
      Important: Use Board Part Files, which did not ends with *_tebf0808
  5. Create XAS and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated


  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup


This does not work, because SD controller is not selected on PS.


Load configuration and Application with Vitis Debugger into device.


QSPI Boot:

  1. Prepare HW like described on section TE0807 Test Board#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

UART0MIO, please select other one, if you have connected uart to second controller or other MIO
PS Interfaces


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

For SDK project creation, follow instructions from:



Template location: ./sw_lib/sw_apps/


TE modified 2020.2 FSBL


  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name


TE modified 2020.2 FSBL


  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • new assembly variants
  • document style update
2020-10-06v.14John Hartfiel
  • new assembly variants
2020-03-25v.13John Hartfiel
  • script update
2020-01-27v.12John Hartfiel
  • Release 2019.2
  • new assembly variants
2019-05-22v.10John Hartfiel
  • Release 2018.3
2019-02-07v.9John Hartfiel
  • new assembly variant


v.7John Hartfiel
  • Release 2018.2
2018-02-08v.5John Hartfiel
  • Release 2017.4
2017-11-14v.3John Hartfiel
  • Release 2017.2

Legal Notices

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Technology Licenses

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