Page History

...

Reason: Updated decoupling capacitor structure according to Xilinx recommendations.

Impact: None. Minor changes in electrical characteristics.

#5 Insert DDR4 testing option (R116, TP9).

...

Reason: Improve module reset and power-up. !!! Add more information!!!

Impact: Changed reset and power-up handling. Please, verify that the module meets your requierements.

#10 Added voltage level translator U29 and resistor R129 as assembly option to connect signal "PHY_LED1" to SoC.

...

Type: Schematic Change

Reason: Change reset voltage threshold from 0.74 V to 0.775 V.

Impact: None. Improve brown-out detection.

#15 Added resistor R132 as assembly option.

...

Reason: Added assembly option for DCI.

Impact: None. Not needed for x16 DDR4.

#16 Change R92 to not assembled.

...

Reason: R92 is not needed.

Impact: None. Not needed for x16 DDR4.

#17 Added power diagram page.

...