Page History
...
Programmable unit | Content | Notes |
|---|---|---|
| Xilinx Artix-7 FPGA | Not programmed | U1 |
| System Controller CPLD | Programmed | U3 |
| SPI Flash OTP area | Empty | U4 |
SPI Flash main array | Empty | U4 |
| SPI Flash Quad Enable bit | Set | U4 |
Microchip 11AA02E48 | Globally unique EUI-48 (Ethernet MAC address) | U7 |
| Programmable quad clock generator, Silicon Labs Si5338 | Programmed, CLK1A - 50M, CLK2 - 125M, CLK3 - 50M | U2 |
Signals, Interfaces and Pins
...
Overview
Content Tools