TE0712 TRM

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Overview

Trenz Electronic TE0712 is a FPGA module integrating an AMD Artix-7 FPGA, with a Quad GTP transceiver, DDR3 SDRAM, QSPI flash memory for configuration and operation. The SoM implements a 10/100 Mbit Ethernet transceiver and powerful switching-mode power supplies for all on-board voltages. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Refer to http://trenz.org/te0712-info for the current online version of this manual and other available documentation.

Key Features

FPGA
- AMD Artix 7 FPGA
  - Device: XC7A15T / XC7A35T / XC7A50T / XC7A75T / XC7A100T / XC7A200T ¹⁾
  - Temperature ranges: Commercial / Extended / Industrial ¹⁾
  - Speed grades: -1 / -2 / -3 ¹⁾
  - Package: FGG484 / FBG484 ²⁾
RAM/Storage
- 1 GByte DDR3 SDRAM ¹⁾
- 32 MByte QSPI Flash ¹⁾
- EEPROM with unique "EUI-48 ™ Node Identity" / MAC address and 192 Byte usable storage
On Board
- 10/100 Mbit Ethernet PHY
- Pre-programmed Clock Generator
  - GTP Transceiver clock
  - Fabric clock
- 25 MHz Oscillator
- User configurable LEDs
- System Controller (SC)
Interface
- 3 x B2B Connector (LSHM) for Trenz 4 x 5 SoM socket
  - 4x GTP MGTs ³⁾
  - XC7A15T / XC7A35T / XC7A50T: 128x SE / 63x DIFF HR IOs
  - XC7A75T / XC7A100T / XC7A200T: 158x SE / 78x DIFF HR IOs
- U.FL connector for SC clock
Power
- System management and power sequencing
- Voltage monitoring
- On-board DCDC converters
Dimension
- 50 mm × 40 mm
Notes
¹⁾ Assembly variant dependent.
²⁾ Sockets FGG484 and FBG484 are footprint-compatible.
³⁾ Data rate depends on package and speed grade.

Block Diagram

TE0712 block diagram

Main Components

TE0712 main components

AMD Artix-7 FPGA series, U1
DDR3 SDRAM, U15, U19
QSPI Flash, U4
EEPROM, U7
System Controller, U3
10/100 Mbps Ethernet PHY transceiver, U5
Programmable Clock Generator, U2
Oscillator, U9 - 25 MHz
DCDC, U14
DCDC, U6, U16
LDO, U8
Voltage monitoring, U10, U11
Samtec Razor Beam™ LSHM B2B connectors, JM1, JM2, JM3
U.FL jack, J1
LEDs, green and red, D1, D2
Load Switch, Q1

Initial Delivery State

Storage device name	Content	Notes
DDR3 SDRAM, U15, U19	Not programmed
QSPI Flash, U4	Not programmed
Programmable Clock Generator, U2	Configuration	Refer to Programmable Clock Generator for more information.
EEPROM, U7	Not programmed	Contains write protected Unique Node ID / MAC .
System Controller, U3	Firmware	Refer to TE0712 CPLD Firmware / TE0712 CPLD for more information.

Initial delivery state of programmable devices on the module

Programmable Clock Generator

The programmable Clock Generator (Si5338A) is used to generate four different clocks from 25 MHz oscillator connected to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B connector JM3 (CLKIN2).

The Si5338 output frequency to the FPGA clocks can be programmed while the Ethernet clock must remain at 50 MHz. An I2C bus is physically connecting the FPGA (master) and clock generator (slave). The I2C logic needs to be created in the FPGA to use this capability. Refer to TE0712 Reference Designs for more information.

CLK Output \| Net Name \| Destination Device.Pin	Default Frequency in MHz	IO Standard	Notes
CLK0A/B \| CLK0_P/N \| U1F.K4/J4	100	LVDS18 ^*	DDR interface
CLK1A \| CLK50M \| U5.23	50	CMOS33	PHY chip RMII reference clock.
CLK1B \| CLK50M2 \| U1E.R4	50	CMOS33 ^*	DDR interface
CLK2A/B \| CLK2_P/N / MGT_CLK0_P/N \| U1H.F6/E6	125	LVDS18	GTP transceiver clock.
CLK3A/B \| PLL_CLK_P/N \| U1F.H4/G4	50	LVDS18	DDR interface

^* Since SoM REV02.

Clock Generator output configuration

Signals, Interfaces and Pins

Connectors

Connector Type	Designator	Interface	IO CNT
B2B	JM1	IO	48x SE / 24x DIFF
B2B	JM1	IO	10x SE / 5x DIFF ¹⁾
B2B	JM1	IO	8x SE / 4x DIFF
B2B	JM1	ETH MDI	4x DIFF
B2B	JM2	IO	48x SE / 24x DIFF
B2B	JM2	IO	18x SE / 9x DIFF
B2B	JM2	IO	2x SE
B2B	JM2	JTAG	4x SE
B2B	JM3	IO	20x SE / 10x DIFF ¹⁾
B2B	JM3	MGT GTP	4x DIFF
B2B	JM3	Clock in MGT GTP	1x DIFF
B2B	JM3	Clock in	1x DIFF
B2B	JM3	IO	4x SE / 2x DIFF
U.FL	J1	IO	1x SE

¹⁾ Only for variants with XC7A75T / XC7A100T / XC7A200T.

Board Connectors

Test Points

Test Point	Signal	Notes
TP1	VIN
TP2	1V
TP3	VTTREF
TP4	3.3VIN
TP5	1.2V_MGT
TP6	GND
TP7	3.3V
TP8	VCCIO13	FPGA bank IO voltage.
TP9	GND
TP10	1.8V
TP11	VCCIO15	FPGA bank IO voltage.
TP12	GND
TP13	1.5V
TP14	VCCIO16	FPGA bank IO voltage.
TP15	GND
TP16	GND
TP17	RESIN
TP18	JTAGEN	JTAG enable. Select JTAG access between FPGA (low) or SC (high).
TP19	TMS
TP20	TDI
TP21	TDO
TP22	TCK
TP23	DCDC_SCL
TP24	DCDC_SDA
TP25	PG_ALL

Test Points Information

On-board Peripherals

Chip/Interface	Designator	Connected To	Notes
FPGA	U1	System Controller, U3 Ethernet PHY, U5 DCDC Power SoC, U14 Clock Generator, U2 DDR3 SDRAM, U15, U19 QSPI Flash, U4 EEPROM, U7 B2B connector, JM1, JM2, JM3
DDR3 SDRAM	U15 / U19	FPGA, U1
QSPI Flash	U4	FPGA, U1
EEPROM	U7	FPGA, U1	Contains unique Node Identity / MAC.
System Controller	U3	FPGA, U1 B2B connector, JM1, JM2 U.FL connector, J1 DCDC Power SoC, U14	Refer to TE0712 CPLD Firmware for more information.
Ethernet PHY	U5	FPGA, U1 Clock Generator, U2 B2B connector, JM1
Clock Generator programmable	U2	FPGA, U1 Ethernet PHY, U5 Oscillator, U9 B2B connector, JM3	Refer to chapter Initial Delivery State / Programmable Clock Generator for more information.
Voltage monitor	U10 / U11	System Controller, U3
Oscillator	U9	Clock Generator, U2

On board peripherals

Configuration and System Control Signals

Signal Name	Connector.Pin	Direction¹⁾	Description
EN1	JM1.28	IN ²⁾	Power enable. ^{2), 3)}
PGOOD	JM1.30	INOUT ²⁾	Power good signal.^{2), 3)}
MODE	JM1.32	INOUT ²⁾	Mode signal. ^{2), 3)}
NOSEQ	JM1.7	INOUT ²⁾	Power sequence signal. ^{2), 3)}
JTAGEN	JM1.89	IN	JTAG selection signal. Low → JTAG access FPGA High → JTAG access System Controller
RESIN	JM2.18	IN ²⁾	Reset signal. ^{2), 3)}
ULI_CPLD	J1.1	OUT ²⁾	System Controller clock signal. ²⁾
TMS / TDI / TDO / TCK	JM2.93 / JM2.95 / JM2.97 / JM2.99	Signal dependent	JTAG.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ Firmware dependent. Refer to TE0712 CPLD for more information.

³⁾ Refer to 4 x 5 SoM Integration Guide for more general information.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾	Notes
VIN	JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8	IN	Module main power supply.
3.3VIN	JM1.13 / JM1.15	IN	Module management power supply.
3.3V	JM1.14 / JM2.10 / JM2.12	OUT	Module 3.3 V power supply.
1.8V	JM1.39	OUT	Module 1.8 V power supply.
1.5V	JM2.19	OUT	Module 1.5 V power supply.
VCCIO13	JM2.1 / JM2.3	IN	FPGA IO bank power supply.
VCCIO15	JM2.7 / JM2.9	IN	FPGA IO bank power supply.
VCCIO16	JM1.9 / JM1.11	IN	FPGA IO bank power supply.
VREF_JTAG / 3.3V	JM2.91	OUT	JTAG reference voltage.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Module power rails.

Recommended Power up Sequencing

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration SoM signal setup.	See Configuration and System Control Signals.
1	3.3VIN	3.3 V (± 5 %)	-	Main (management) power supply.	Power consumption depends mainly on design and cooling solution.
2	VIN	3.3 V (± 5 %) ¹⁾	-	Main power supply.	Power consumption depends mainly on design and cooling solution.
3	EN1	3.3 V (± 5 %)	PU, 3.3 V ²⁾	Power release.	Controlled module internally. Can be used to disable power. Tie only to GND or leave floating.
4	3.3V or PGOOD ³⁾	3.3 V (± 5 %) 3.3 V (± 5 %)	- ³⁾	Module generated output voltage/signal.	This voltage/signal ³⁾ can be used to supply bank voltages, to supply periphery and/or as power good signal to enable external power regulators. Important: Consider maximum power consumption.
5	VCCIO13 ⁴⁾ / VCCIO15 ⁴⁾ / VCCIO16 ⁴⁾	-	-	Module bank voltages.

Baseboard Design Hints

¹⁾ A higher or lower input voltage may be possible.

²⁾ (on module)

³⁾ Firmware dependent. Refer to TE0712 CPLD Firmware / TE0712 CPLD for more information.

⁴⁾ Caution: A voltage difference between supply rails V_CCO and V_CCAUX of more than 2.625 V has to be temporarily limited to below T_VCCO2VCCAUX for each power-on/off cycle. Refer to AMD data sheet DS181 for more information.

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)

Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order number	Connector on baseboard	compatible to	Mating height
23836	REF-189016-01	LSHM-150-02.5-L-DV-A-S-K-TR	6.5 mm
	LSHM-150-03.0-L-DV-A-S-K-TR	LSHM-150-03.0-L-DV-A-S-K-TR	7.0 mm
23838	REF-189016-02	LSHM-150-04.0-L-DV-A-S-K-TR	8.0 mm
	LSHM-150-06.0-L-DV-A-S-K-TR	LSHM-150-06.0-L-DV-A-S-K-TR	10.0mm
26125	REF-189017-01	LSHM-130-02.5-L-DV-A-S-K-TR	6.5 mm
	LSHM-130-03.0-L-DV-A-S-K-TR	LSHM-130-03.0-L-DV-A-S-K-TR	7.0 mm
24903	REF-189017-02	LSHM-130-04.0-L-DV-A-S-K-TR	8.0 mm
	LSHM-130-06.0-L-DV-A-S-K-TR	LSHM-130-06.0-L-DV-A-S-K-TR	10.0mm

Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking height	Speed rating
12 mm, Single-Ended	7.5 GHz / 15 Gbps
12 mm, Differential	6.5 GHz / 13 Gbps
5 mm, Single-Ended	11.5 GHz / 23 Gbps
5 mm, Differential	7.0 GHz / 14 Gbps

Speed rating.

Current Rating

Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings

Shock: 100G, 6 ms Sine
Vibration: 7.5G random, 2 hours per axis, 3 axes total

Manufacturer Documentation

	File	Modified
	PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File lshm_dv.pdf LSHM catalog page	Apr 07, 2016 by Thorsten Trenz
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	PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File REF-189016-01.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File REF-189016-02.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
	Labels Preview View
	PDF File REF-189017-01.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File REF-189017-02.pdf Technical Drawing	Apr 07, 2016 by Thorsten Trenz
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	PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report	Apr 07, 2016 by Thorsten Trenz
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	PDF File tc0929--2611_qua(1).pdf Shock and vibration report	Apr 07, 2016 by Thorsten Trenz
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Technical Specifications

This TRM is generic for all variants.

The voltage ranges are generally the same across variants (exceptions are possible, depending on custom requests).
The temperature range can differ depending on the assembly version.
The combination of a carrier and a SoM might have different requirements.

Variants of modules are described here: Article Number Information. Please contact us for options.

Absolute Maximum Ratings ^*)

Power Rail Name / Schematic Name	Description	Min	Max	Unit
VIN	Main power supply.	-0.3	6.5	V
3.3VIN	Main (management) power supply.	-0.3	3.6	V
VCCIO13	FPGA Bank 13 power supply.	-0.5	3.6	V
VCCIO15	FPGA Bank 15 power supply.	-0.5	3.6	V
VCCIO16	FPGA Bank 16 power supply.	-0.5	3.6	V

Absolute maximum ratings

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

Modules with commercial temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
Modules with extended temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
Modules with industrial temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

Customer SoC/FPGA design.
Cooling solution, active and or passive cooling.
Climate or environmental conditions besides ambient temperature range.
Module orientation, neighbouring assemblies, neither other heat sources nor the SoC/FPGA as heat source to other components.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components.

The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

Parameter	Min	Max	Units
VIN	3.135	5.25	V
3.3VIN	3.201	3.399	V
VCCIO13	1.164	3.399	V
VCCIO15	1.164	3.399	V
VCCIO16	1.164	3.399	V

Recommended operating conditions.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.6 mm ±10 %
Mating height with standard connectors: 8 mm

All dimensions are shown in millimeters.

Physical Dimension

Currently Offered Variants

Trenz shop TE0712 overview page*
English page	German page

*) Module article name encoding table: 7 Series Spartan, Artix and Kintex modules

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

The hardware revision number is located on the PCB next to the module identifier, separated by a dash.

Board hardware revision number.

Date

Revision

Changes

Documentation Link

2022-11

03

1. Added Legal notices, project overview and revision changes. Updated page count and page order.
2. Added a D3 diode between the INIT and PROG_B signals to keep the FPGA in the reset state while PROG_B is low during the initial power-up.
3. Resistors R2, R68 replaced by 2K2 (were 4K87) to improve I2C stability at higher baud rates.
4. Change obsolete ferrite beads BKP0603HS121-T to MPZ0603S121HT000 for L1, L2, L3, and L5.
5. Revised power supply circuit. Change obsolete components:
- EN63A0QI to MP8869SGL-Z ( U14 )
- EP53F8QI to MPM3834CGPA ( U6, U16 )
6. Change Q1 power switch TPS27082LDDCR to MP5077GG-Z.
7. Added power monitors U10, U11 STM6710LWB6F. System controller pin U3.25 connected to net PG_ALL instead of 3.3V.
8. U14 I2C interface connected to bus PLL_SDA / PLL_SCL U1B. Connect U14 to I2C bus via resistors R80 and R81 and pull-up resistors R26 and R27 and test points TP23 and TP24. Added table with device addresses on the I2C bus. A new device will be detected during a bus scan.
9. Change capacitors in net "VIN" from 47 uF, 6.3 V to 22 uF, 10 V for C70, C80, C126, C127, C132, C176, C177.

10. Change resistor values for R62 from 2.49 kOhm to 4.99 kOhm and for R63 from 4.99 kOhm to 10 kOhm.
11. Change capacitors C18, C19, C125, C158, C174.
13. Change SI5338A-B-GM firmware.

REV03

PCN

2016-01

02

1. Added pullup on SPI "hold".
2. Added test points.
3. Routed MII clock pin additionally to FPGA.
4. Routed one more PLL clock output to FPGA.
5. Added I2C SCL Pullup.

6. Change DDR3 RAM (U15, U19) from IM4G16D3FABG-125I to IS43TR16256BL-125KBLI.
7. All SoMs use S25FL256SAGBHI20 Flash (U4).
8. Clock Revision Change (U9) SiT8008AI-73-XXS-25.000000E to SiT8008BI-73-XXS-25.000000E.

REV02

PCN

2014-07

01

Initial revision

REV01

Hardware Revision History

Document Change History

Date	Revision	Contributors	Description
2026-08-26	v.36	Kilian Jahn	DrawIO diagrams - Fixed settings for toolbar and boarder Document change history - Fixed some entries
2025-08-28	v.35	Martin Rohrmüller	Typo + Style
2025-08-01	v.34	Kilian Jahn	Updated to TRM version 4.3.1 Updated TRM to hardware revision 03
2024-04-30	v.33	Martin Rohrmüller	Updated Download link for this document
2022-12-22	v.31	Waldemar Hanemann	Variants will changed to shop search
2020-07-03	v.23	John Hartfiel	add power sequencing notes
2019-01-10	v.22	John Hartfiel	Update document change history Update system controller and power sequencing chapter
2017-12-15	v.18	John Hartfiel	Update Board to Board (B2B) I/Os
2017-12-12	v.15	John Hartfiel	Replace B2B connector section Typo correction on Clocking section
2017-05-29	v.13	Jan Kumann	Variants table added. Key Features section relocated.
2017-03-01	v.7	John Hartfiel	BUGFIX in the description of System Controller I/O section Update Clocking Section
2017-01-26	v.3	Jan Kumann	New block diagram. Few corrections.
2017-01-20	v.2	Jan Kumann	Revised version.
2013-12-02	v.1	Antti Lukats	Work in progress.
--	all	Pedram Babakhani , Thomas Brünger , Antti Lukats , John Hartfiel , Jan Kumann , Kilian Jahn , Martin Rohrmüller , Thorsten Trenz , Waldemar Hanemann	--

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

2025-08-01

Trenz Electronic Documentation