Downloads / Documents
What do the abbreviations on the downloadable documents mean?
You can lookup for file abbreviations on Documents Naming Conventions.
What's is the maximum power consumption of the module?
The maximum power consumption of a module manly depends on the design which is running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to generate power consumption of the developed design with Vivado.
Please also observe the TRM of the Trenz Electronic module and the power management of our corresponding carrier boards.
What's Trenz Electronic Module Life Cycles?
You can lookup Trenz Electronic Micromodules
Where can I find a overview of available modules?
Trenz Electronic Modules are listed on our shop page grouped by FPGA-Family
7 Series FPGAs - LVDS_33, LVDS_25, LVDS_18, LVDS inputs & outputs for High Range (HR) and High Performance (HP) I/O banks
See Xilinx Answer Record: AR# 43989
Xilinx Release Notes and Known Issues
Links to Xilinx Release Notes are available on Vivado/SDK/SDSoC: Xilinx Software-Product Update Release Notes and Known Issues
How can I excecute Trenz Electronic reference designs on Win/Linux?
Reference Designs will be delivered as scripted project file. Vivado Project files will be generated with these scripts.
Windows and Linux (since Vivado 2016.4) start up command files are available to generate the project: Project Delivery QuickStart
All other options are described on: Vivado Projects
Where can I find Trenz Electronic Board Part Files? And how can select and use the correct one for may assembly option?
Which devices are supported by Xilinx Vivado HL WebPACK Edition?
Xilinx provide a list with supported functionality and devices on: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html
How can I activate beta devices (ES-devices)?
Now Vivado check all Beta Devices, but only Devices with valid license are visible. With Beta Device enable, Vivado need longer startup. Select special beta device is supported too. See Xilinx Forum: Synthesis Failure for ZCU102
"ERROR: [Labtools 27-3165] End of startup status: LOW" after FPGA programming
Insufficient external power supply can cause this issue. If power supply is insufficient, module restarts and FPGA content is erased. Vivado did not recognize this.
"ERROR: [Labtools 27-2269] No devices detected on target localhost:..." after JTAG connection via Vivado HW-Manager
Please check following: