- Created by Thorsten Trenz, last modified by John Hartfiel on 08 02, 2023
Trenz Products |
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What is the EOL of the products manufactured by Trenz Electronic? EOL of our module series is normally as long as Xilinx and Intel will offer the FPGA/SoC: Passive components (resistors, capacitors) or components which will not influence the FPGA or HW design can be changed on the modules without notification. We use different manufacturer and best prices, but in any case the characteristics which are specified in the schematics are the same. In case other active components will be not longer available, we will replace with footprint compatible equivalent alternatives or we update the PCB to support a equivalent alternatives variant. In case we change such a component, we will create also a new article number, so that you can directly see that something was be updated and we write a PCN |
Trenz Electronic Article Number Trenz Electronic provides Module series with different assembly options (FPGA size, speed grade, temperature range, DDR size, QSPI size, eMMC size, less components, different stacking height...) |
Xilinx SoC/FPGA package marking Xilinx device information can be requested with the 2D Bare code or Lot code on the device package. This can be done via Xilinx App:
Or over web page: In both cases a Xilinx login is needed. |
General Copyright Deviations from the general copyrights, if any, are indicated at the corresponding boards. If not the following applies: Copyright for most board with SoC/FPGA (Modules / Motherboards...):
Copyright for most Carrier:
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Downloads / Documents |
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What do the abbreviations on the downloadable documents mean? You can lookup for file abbreviations on Documents Naming Conventions. |
Where can I find PCB documentation and download area? PCB document is available on our wiki pages and download area. |
PCB Design |
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Cooling solutions for trenz modules... Cooling solution depends mainly on FPGA design and environment. This must therefore always be considered individually. Trenz Electronic cooling solutions for some modules: Xilinx documentation:
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What's is the maximum power consumption of the module? The maximum power consumption of a module manly depends on the design which is running on the FPGA. Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to generate power consumption of the developed design with Vivado. Please also observe the TRM of the Trenz Electronic module and the power management of our corresponding carrier boards. Other related documentation: |
Where can I find master pinout files for the SOMs? Module pinout files can be generated with our Master Excel Pinout Sheet. You can also use the schematic on our download area. |
7 Series FPGAs - LVDS_33, LVDS_25, LVDS_18, LVDS inputs & outputs for High Range (HR) and High Performance (HP) I/O banks See Xilinx Answer Record: AR# 43989 |
Power sequencing for variable IO banks and connected periphery Power sequencing of the FPGA/SoC banks and IOs must be still fulfil restrictions from manufacturer data sheet. In most case IOs should be enabled after core voltages are powered on. Some module output voltage can be used to enable carrier power regulator for variable bank powers and connected periphery. See also data-sheet power sequencing of the section of the give device: 7 Series:
U/U+ Series:
U+ RFSoC Xilinx AR#
Xilinx Forum |
How do I extract the libraries from the Altium project of carriers? Use in Altium, Design → "Create integrated library" It will recreate all used lib symbols |
TE0803/07/08 connector alingment problem (SS5-80-xxxx-L-D-K-TR) These connectors do not self align, so the placement has to be good initially. Connectors should be placed with 50µm accuracy. Not every assembly house can do this. However even with higher tolerances, the connection is normally stable. Furthermore we discussed with Samtec and got following hints:
As we saw the alignment issue with a few customers, we decided to make a sister series of TE0803, TE0807, TE0808 with other connectors. |
Vivado/SDK/SDSoC/PetaLinux |
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Xilinx Release Notes and Known Issues Links to Xilinx Release Notes are available on Vivado/SDK/SDSoC: Xilinx Software-Product Update Release Notes and Known Issues |
How can I excecute Trenz Electronic reference designs on Win/Linux? Reference Designs will be delivered as scripted project file. Vivado Project files will be generated with these scripts. Windows and Linux (since Vivado 2016.4) start up command files are available to generate the project: Project Delivery QuickStart All other options are described on: Vivado Projects - TE Reference Design |
Where can I find Trenz Electronic Board Part Files? And how can select and use the correct one for may assembly option? Trenz Electronic Board Part Files will be delivered with the reference designs on our download area.They ca be installed in different ways.
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Where can I find documentation of Xilinx Software? Xilinx Documentation is available on Xilinx Hompage. Some helpful documentation and Links are available on AMD Development Tools |
Where can I find PetaLinux BSP for my module? We provide PetaLinux template projects instead of BSPs for our modules. This template are included in our reference design in the subfolder (os/petalinux). They are available on our download area. You can lookup for instructions on: PetaLinux KICKstart |
Which devices are supported by Xilinx Vivado HL WebPACK Edition? Xilinx provide a list with supported functionality and devices on: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html |
How can I activate beta devices (ES-devices)?
Now Vivado check all Beta Devices, but only Devices with valid license are visible. With Beta Device enable, Vivado need longer startup. Select special beta device is supported too. See Xilinx Forum: Synthesis Failure for ZCU102 |
"ERROR: [Labtools 27-3165] End of startup status: LOW" after FPGA programming Insufficient external power supply can cause this issue. If power supply is insufficient, module restarts and FPGA content is erased. Vivado did not recognize this. |
"ERROR: [Labtools 27-2269] No devices detected on target localhost:..." after JTAG connection via Vivado HW-Manager Please check following:
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QSPI Flash access in QUAD Read mode failed Check if the Quad Enable (QE) bit in the Configuration Register of the flash is set to 1. If the QE-Bit is set or not depends on the last access to the flash.
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