Page History
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| CLK Output | FPGA Bank | FPGA Pin | IO Standard | Net Name | Default Frequency | Notes |
|---|---|---|---|---|---|---|
| CLK0 | 35 | K4/J4 | DIFF_SSTL15 | CLK0_P/N | Off | NB! Since PCB REV02. |
| CLK1A | - | - | CLK50M | 50 MHz | PHY chip RMII reference clock. | |
| CLK1B | 34 | R4 | CLK50M2 | --Off | NB! Since PCB REV02. | |
| CLK2 | 216 | F6/E6 | Auto | MGT_CLK0_P/N | 125 MHz | GTP transceiver clock. |
| CLK3 | 35 | H4/G4 | DIFF_SSTL15 | PLL_CLK_P/N | 50 MHz |
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Overview
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