Page History
Template Revision 2.8 - on construction
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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
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- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
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Table of contents
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Overview
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Notes :
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Zynq PS Design with DDR Less FSBL Example.
Refer to http://trenz.org/te0722-info for the current online version of this manual and other available documentation.
Key Features
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Notes :
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- 2019.2 update
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- split FSBL into 2 templates, one with and one without Sensor+LED access example app
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- TE Script update
- rework of the FSBLs
- DDR LESS, Device ID, Sensor+LED access
- VIO for RGB access
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- initial release
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- Option1:
- In case Flash is empty, use fsbl_flash on programming GUI
- In case Flash is programmed use normal fsbl on programming GUI
- Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
Requirements
Software
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- list of software which was used to generate the design
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
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Design supports following carriers:
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Additional HW Requirements:
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for JTAG, UART
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
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Additional Sources
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Prebuilt
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Notes :
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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File
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File-Extension
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Vivado HW Manager
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Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- Enable/Disable RGB LED Counter (default on)
- Enable/Disable different colors (default all off)
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System Design - Vivado
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Block Design
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Source location: \sw_lib\sw_apps
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Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
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- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
zynq_fsbl_app
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
- Disable Memory initialisation on main.c
Module Specific:
- Add Files: all TE Files start with te_*
- Example app for LED access over MIO and sensor access over I2C
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
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Overview
Content Tools