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Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board"

DateVersionChangesAuthor
2022-06-152.2
  • add 'QSPI-Boot mode'
  • add 'Get prebuilt boot binaries'
  • changed SD-Boot mode chapter
  •  'Device Tree' chapter expanded
TD
2022-04-212.1
  • update to 21.x
TD
2022-02-282.0
  • add yocto to
    • Overview → Key Features
    • Overview → Requirements
    • Design Flow
    • Launch
  • add section 'Software Design - Yocto'
TD
2021-06-151.2
  • table of content view
  • template history
  • placed a horizontal separation line under each chapter heading
  • replaced <design name> by <project folder>
  • changed title-alignment for tables from left to center
  • update 19.x to 20.x
JH,TD
2020-11-241.1
  • add fix table of content
  • add table size as macro
JH
--1.0----


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if quartus revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
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        sortEnabledfalse
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        ExampleComment
        12



  • ...

Overview

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Notes :

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Libero SoC v2022.2
  • SoftConsole v2022.2-RISC-V-747
  • PolarfireSoC MSS Configurator v2022.2
  • HSS (Hardware System Service)
  • Yocto
  • UART
  • ETH
  • USB
  • I2C
  • QSPI flash
  • DDR3 memory
  • User LED

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


Scroll Title
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titleDesign Revision History

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DateLibero SoCProject BuiltAuthorsDescription
2023-04-30v2022.2


Mohsen Chamanbaz
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


Scroll Title
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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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titleSoftware

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SoftwareVersionNote
Libero SoCv2022.2needed
SoftConsolev2022.2needed
PolarfireSoC MSS Configuratorv2022.2needed
YoctoKirkstoneneeded (more information: Yocto KICKstart#Used source files)


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

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Module ModelBoard Part Short NameYocto Machine NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TEM0007*??????tem0007REV011GB64MB------------

*used as reference

Design supports following carriers:

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Carrier ModelNotes
TEM0703*As carrier board. This board must be special for Microchip FPGAs.

*used as reference

Additional HW Requirements:

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Additional HardwareQuantityNotes
TE0790 XMOD1For HSS console
Mini USB cable for JTAG/UART2Check Carrier Board and Programmer for correct type
RJ45 Ethernet cable1

*used as reference

Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Microchip devices

Design Sources

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TypeLocationNotes
Libero

<project folder>/source_files/Libero

<project folder>/source_files/<Board Part Short Name>/Libero

Libero project will be generated by TE Scripts

(Optional) Source files for specific assembly variants

SoftConsole

<project folder>/source_files/SoftConsole

<project folder>/source_files/<Board Part Short Name>/SoftConsole

Additional software will be generated by TE Scripts

(Optional) Source files for specific assembly variants

Yocto<project folder>/source_files/os/yoctoYocto BSP layer template for linux


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      Libero Project File*.prjx
      FlashPro Express Job*.job
      Constraint File*.pdc
      Timing Constraint File*.sdc
      Components in Block Design*.cxf
      Configuration File*.cfg



      Software-Application-File*.elfSoftware application for SoftConsole



      Device Tree

      *.dtbDevice tree blob
      CONF-File*.confBoot configuration file (extlinux.conf)
      Yocto linux image*.wicThis File can be flashed via bmaptool on the SD card.
      Yocto linux image*.imgLinux image for SD card




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File

File-Extension

Description

Libero Project File*.prjx
FlashPro Express Job*.job
Constraint File*.pdc
Timing Constraint File*.sdc
Components in Block Design*.cxf
Configuration File*.cfg



Software-Application-File*.elfSoftware application for SoftConsole



Device Tree

*.dtbDevice tree blob
CONF-File*.confBoot configuration file (extlinux.conf)
Yocto linux image*.wicThis File can be flashed via bmaptool on the SD card.
Yocto linux image*.imgLinux image for SD card


Download

Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Libero Design Flow.

See also:

Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed. The user needs only to write the image file on the SD card. To prepare the image file :

  1. Download and save meta-trenz-polarefile-bsp folder in the host linux
  2. Expand
    titleIn meta-trenz-polarfire-bsp execute shell script via the following command:
    Code Block
    themeMidnight
    linenumberstrue
    	. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh
  3. Expand
    titleEnter the machine name. Here the machine is equal to module name , but with lower case letters. For example for TEM0007 module enter : tem0007

    Image Removed

  4. Expand
    titleEnter the image type. It depends on the user application and required installed packages in linux. As default the user can enter: te-image-minimal

    Image Removed

  5. After compiling image file *.img and its converted zip file *.zip will be in trenz bsp folder saved :
    • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
    • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip

Launch

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The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.

The "normal" Libero project will be generated in the subfolder "/Libero/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.

To create project do the following steps:

  1. Execute "create_project_win.cmd" or "create_project_linux.sh"
  2. Select your board in "Board selection" , if there is more than one variant.
  3. Choose one of the following options::
    1. Press 0 , if it will enter the full path of Libero SoC TCL shell.
    2. Press 1, if it will enter the full path of Microchip installation folder. For example "c:\Microchip\"
    3. Press 2, if it will enter folder path or drive to search for variable TCL shell and select from generated list elements.
    4. Press x to exit script.
  4. Choose one of the following options:
    1. Press 0 to use Libero SoC at its path. For example Libero_SoC_v2022.2 at C:/Microchip/Libero_SoC_v2022.2
    2. Press 1 to enter path of installation folder of Microchip or Libero SoC
    3. Press 2 to enter full path of Libero SoC exe file
    4. Press 3 to exit th script
  5.  Choose one of the following options:
    1. Press 0 to overwrite old Libero project folder , if it exists.
    2. Press 1 to to generate another project folder
    3. Press 2 to to enter own Libero project folder name
    4. Press 3 to exist script and do not generate the hardware design
  6. Waiting to be completed the generation of new project , if a new project is desired.
  7. Press y to open the generated Libero SoC project.

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Get prebuilt boot binaries

Note

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

  1. Run create_project_win.cmd/create_project_linux.sh
  2. Select Module in 'Board selection'
  3. Click on 'Export prebuilt files' button
    1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

SD-Boot mode

Prepare SD card as follows for SD-Boot.

There are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:

    1. Insert SD card in the SD card reader
    2. Expand
      titlebmaptool command
      Code Block
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      bmaptool copy --nobmap <Path of image file *.img>  /dev/sdX

      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
    3. Expand
      titledd command
      Code Block
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      dd if=<Path of image file *.img> of=/dev/sdX
      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.

Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.

JTAG

Not used on this example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Connect your board to the network
  4. Power on PCB

UART

  1. Open Serial Console (e.g. PuTTY)
    1. select COM Port

      Info

      Win OS: see device manager

      Linux OS: see  dmesg | grep tty  (UART is *USB1)


    2. Speed: 115200
  2. Press reset button
  3. Console output depends on used Software project, see Software Design - SDK#Application
  4. Linux Console:
    1. Login data:

      Info

      Note: Wait until Linux boot finished


      Code Block
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      tem0007 login: root
      


    2. You can use Linux shell now.

      Code Block
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      i2cdetect -y -r 1   (check I2C 1 Bus)
      dmesg | grep rtc    (RTC check)
      udhcpc              (ETH0 check)
      lsusb               (USB check)


  5. ...

System Design - Libero

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Note:

  • Description of Block Design - Project, Block Design - Platform Designer, ... Block Design Pictures from Export...

Block Design

The block designs may differ depending on the assembly variant.

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titleBlock Design - Project


Scroll Title
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titleBlock Design - Platform Desginer

HPS Interfaces

Activated interfaces:

TypeNote
DDR--
EMAC0--
EMAC1--
GPIO0--
GPIO1--
GPIO2--
I2C0--
I2C1--
QSPI--
SDMMC--
UART0--
UART1--
USB0--
USB1--
CAN0--
CAN1--


Software Design - SoftConsole

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Note:
  • optional chapter separate

  • sections for different apps

Application

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----------------------------------------------------------

General Example:

hello_tei0006

Hello TEI0006 is a Hello World example as endless loop instead of one console output.

Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

...

Software Design - Yocto

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----

General Example:

hello_tei0006

Hello TEI0006 is a Hello World example as endless loop instead of one console output.

Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

...

Software Design - Yocto

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Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed. The user needs only to write the image file on the SD card. To prepare the image file :

  1. Download and save meta-trenz-polarefile-bsp folder in the host linux
  2. Expand
    titleIn meta-trenz-polarfire-bsp execute shell script via the following command:
    Code Block
    themeMidnight
    linenumberstrue
    	. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh
  3. Expand
    titleEnter the machine name. Here the machine is equal to module name , but with lower case letters. For example for TEM0007 module enter : tem0007

    Image Added

  4. Expand
    titleEnter the image type. It depends on the user application and required installed packages in linux. As default the user can enter: te-image-minimal

    Image Added

  5. After compiling image file *.img and its converted zip file *.zip will be in trenz bsp folder saved :
    • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
    • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip

For Yocto installation and project creation, follow instructions from:

U-Boot

Start with Create a custom BSP layer for Microchip SoC or FPGA#Configure u-boot

File location: meta-<module>/recipes-bsp/u-boot/

Changes:

  • No changes

Device Tree

U-boot Device Tree

Code Block
languagejs
titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-bsp/u-boot/files/<module_series>_<Board_Part_Short_Name>/dts/<module_series>_<Board_Part_Short_Name>.dts
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/dts-v1/;

#include "microchip-mpfs.dtsi"
#include "dt-bindings/gpio/gpio.h"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	aliases {
		serial1 = &uart1;
		ethernet0 = &mac0;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial1";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg CLK_DDRC>;
		status = "okay";
	};
        
};

&uart1 {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-mmc-highspeed;
	cap-sd-highspeed;
    cd-debounce-delay-ms;
	card-detect-delay = <200>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;

};



&mac1 {
	status = "disabled";
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
        reset-names = "ETH_RST";
        reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};



&qspi {
	status = "okay";
	num-cs = <1>;
	flash0: spi-nor@0 {
		compatible = "spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		spi-cpol;
		spi-cpha;
	};
};
 


Kernel Device Tree

Code Block
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titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-kernel/linux/files/dts/<module_series>_<Board_Part_Short_Name>.dts
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ		1000000

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit",
		     "microchip,mpfs";

	aliases {
		ethernet0 = &mac0;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	cpus {
		timebase-frequency = <MTIMER_FREQ>;
	};
    


    //******************************************************//
    
    ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		status = "okay";
	};
    
    reserved-memory {	
        #address-cells = <2>;
		#size-cells = <2>;
        
		ranges;
        
		fabricbuf0ddrc: buffer@A0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xA0000000 0x0 0x2000000>;
			no-map;
		};
	};
    
	udmabuf0 {
		compatible = "ikwzm,u-dma-buf";
		device-name = "udmabuf-ddr-c0";
		minor-number = <0>;
		size = <0x0 0x2000000>;
		memory-region = <&fabricbuf0ddrc>;
		sync-mode = <3>;
	};
    
    
    //******************************************************//
    
    usb_phy: usb_phy {
    	#phy-cells = <0>;
        //compatible = "ulpi-phy";
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
        reset-names = "OTG_RST";
    };
    
    
	soc {
	};
};

&can0 {
	status = "disabled";
};

&core_pwm0 {
	status = "okay";
};


&fpgadma {
	status = "okay";
};

&fpgalsram {
	status = "okay";
};

&gpio1 {
    status = "okay";
};

&gpio2 {
	interrupts = <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";    
	#address-cells = <1>;
    #size-cells = <0>;

	eeprom: eeprom@50 {
    	compatible = "atmel,24c02";
        reg = <0x50>;
        #address-cells = <1>;
        #size-cells = <1>;        
        eth0_addr: eth-mac-addr@FA {
            reg = <0xFA 0x06>;
        };
    };
};

&i2c2 {
	status = "okay";       
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";    
	nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";    
	/delete-property/ local-mac-address;    
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
		reset-names = "ETH_RST";
		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};

&mac1 {
	status = "disabled";
};


&mbox {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};


&qspi {
	status = "okay";
    num-cs = <1>;
};

&refclk {
	clock-frequency = <125000000>;
};


&spi0 {
	status = "okay";
};

&spi1 {
	status = "disabled";
};


&usb {
	status = "okay";
	dr_mode = "otg";  
    phys = <&usb_phy PHY_TYPE_USB2>;
};

 

Kernel

Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernel

File location: meta-<module>/recipes-kernel/linux/

Changes:

  • No changes.

Images

Image recipe for minimal console image

File location: meta-<module>/recipes-images/yocto/

Image recipes:

  • te-image-minimal.bb: create minimal linux image
  • te-initramfs.bb: required for building an image with initial RAM Filesystem

Added packages/recipes:

  • No packages/recipes

Rootfs

Used filesystem: Initial RAM Filesystem (initramfs)

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_dch
title-alignmentcenter
titleDocument change history

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateDocument Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • Initial release v2022.2
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices




Scroll Only


HTML
<style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



Scroll pdf ignore


Custom_fix_page_content

Table of contents

Table of Contents
outlinetrue