TEM0007 Test Board

Overview

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

Key Features

• Libero SoC v2022.2
• SoftConsole v2022.2-RISC-V-747
• PolarfireSoC MSS Configurator v2022.2
• HSS (Hardware System Service)
• Yocto
• UART
• ETH
• USB
• I2C
• QSPI flash
• DDR3 memory
• User LED

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - Microchip devices

Design Sources

Prebuilt

Download

Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.

Reference Design is available on:

• TEM0007 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Libero Design Flow.

See also:

• Project Delivery - Microchip devices

The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.

The "normal" Libero project will be generated in the subfolder "/Libero/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.

To create project do the following steps:

1. Execute "create_project_win.cmd" or "create_project_linux.sh"
2. Select your board in "Board selection" , if there is more than one variant.
3. Choose one of the following options::
   1. Press 0 , if it will enter the full path of Libero SoC TCL shell.
   2. Press 1, if it will enter the full path of Microchip installation folder. For example "c:\Microchip\"
   3. Press 2, if it will enter folder path or drive to search for variable TCL shell and select from generated list elements.
   4. Press x to exit script.
4. Choose one of the following options:
   1. Press 0 to use Libero SoC at its path. For example Libero_SoC_v2022.2 at C:/Microchip/Libero_SoC_v2022.2
   2. Press 1 to enter path of installation folder of Microchip or Libero SoC
   3. Press 2 to enter full path of Libero SoC exe file
   4. Press 3 to exit th script
5.  Choose one of the following options:
   1. Press 0 to overwrite old Libero project folder , if it exists.
   2. Press 1 to to generate another project folder
   3. Press 2 to to enter own Libero project folder name
   4. Press 3 to exist script and do not generate the hardware design
6. Waiting to be completed the generation of new project , if a new project is desired.
7. Press y to open the generated Libero SoC project.

Launch

Programming

Get prebuilt boot binaries

1. Run create_project_win.cmd/create_project_linux.sh
2. Select Module in 'Board selection'
3. Click on 'Export prebuilt files' button
   1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

SD-Boot mode

Prepare SD card as follows for SD-Boot.

There are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:

1. 1. Insert SD card in the SD card reader
   2. bmaptool command

      bmaptool copy --nobmap <Path of image file *.img>  /dev/sdX

      
      
      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
   3. dd command

      dd if=<Path of image file *.img> of=/dev/sdX

      1. After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.

Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Connect your board to the network
4. Power on PCB

UART

1. Open Serial Console (e.g. PuTTY)

   1. select COM Port

      Win OS: see device manager

      Linux OS: see  dmesg | grep tty  (UART is *USB1)

   2. Speed: 115200
2. Press reset button
3. Console output depends on used Software project, see Software Design - SDK#Application
4. Linux Console:

   1. Login data:

      Note: Wait until Linux boot finished

      tem0007 login: root
      

   2. You can use Linux shell now.

      i2cdetect -y -r 1   (check I2C 1 Bus)
      dmesg | grep rtc    (RTC check)
      udhcpc              (ETH0 check)
      lsusb               (USB check)

5. ...

System Design - Libero

Block Design

The block designs may differ depending on the assembly variant.

Block Design - Project

Block Design - Platform Desginer

HPS Interfaces

Activated interfaces:

Software Design - SoftConsole

Application

Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

...

Software Design - Yocto

Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed. The user needs only to write the image file on the SD card. To prepare the image file :

1. Download and save meta-trenz-polarefile-bsp folder in the host linux
2. In meta-trenz-polarfire-bsp execute shell script via the following command:

   	. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh

3. Enter the machine name. Here the machine is equal to module name , but with lower case letters. For example for TEM0007 module enter : tem0007

   

4. Enter the image type. It depends on the user application and required installed packages in linux. As default the user can enter: te-image-minimal

   

5. After compiling image file *.img and its converted zip file *.zip will be in trenz bsp folder saved :

• • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
  • <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip

For Yocto installation and project creation, follow instructions from:

• Yocto KICKstart
• Create a custom BSP layer for Microchip SoC or FPGA

U-Boot

Start with Create a custom BSP layer for Microchip SoC or FPGA#Configure u-boot

File location: meta-<module>/recipes-bsp/u-boot/

Changes:

• No changes

Device Tree

U-boot Device Tree

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 Microchip Technology Inc.
 * Padmarao Begari <padmarao.begari@microchip.com>
 */

/dts-v1/;

#include "microchip-mpfs.dtsi"
#include "dt-bindings/gpio/gpio.h"

/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ		1000000

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	aliases {
		serial1 = &uart1;
		ethernet0 = &mac0;
		spi0 = &qspi;
	};

	chosen {
		stdout-path = "serial1";
	};

	cpus {
		timebase-frequency = <RTCCLK_FREQ>;
	};

	ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg CLK_DDRC>;
		status = "okay";
	};
        
};

&uart1 {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-mmc-highspeed;
	cap-sd-highspeed;
    cd-debounce-delay-ms;
	card-detect-delay = <200>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;

};



&mac1 {
	status = "disabled";
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
        reset-names = "ETH_RST";
        reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};



&qspi {
	status = "okay";
	num-cs = <1>;
	flash0: spi-nor@0 {
		compatible = "spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		spi-cpol;
		spi-cpha;
	};
};
 

Kernel Device Tree

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ		1000000

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit",
		     "microchip,mpfs";

	aliases {
		ethernet0 = &mac0;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	cpus {
		timebase-frequency = <MTIMER_FREQ>;
	};
    


    //******************************************************//
    
    ddrc_cache: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		status = "okay";
	};
    
    reserved-memory {	
        #address-cells = <2>;
		#size-cells = <2>;
        
		ranges;
        
		fabricbuf0ddrc: buffer@A0000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xA0000000 0x0 0x2000000>;
			no-map;
		};
	};
    
	udmabuf0 {
		compatible = "ikwzm,u-dma-buf";
		device-name = "udmabuf-ddr-c0";
		minor-number = <0>;
		size = <0x0 0x2000000>;
		memory-region = <&fabricbuf0ddrc>;
		sync-mode = <3>;
	};
    
    
    //******************************************************//
    
    usb_phy: usb_phy {
    	#phy-cells = <0>;
        //compatible = "ulpi-phy";
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
        reset-names = "OTG_RST";
    };
    
    
	soc {
	};
};

&can0 {
	status = "disabled";
};

&core_pwm0 {
	status = "okay";
};


&fpgadma {
	status = "okay";
};

&fpgalsram {
	status = "okay";
};

&gpio1 {
    status = "okay";
};

&gpio2 {
	interrupts = <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";    
	#address-cells = <1>;
    #size-cells = <0>;

	eeprom: eeprom@50 {
    	compatible = "atmel,24c02";
        reg = <0x50>;
        #address-cells = <1>;
        #size-cells = <1>;        
        eth0_addr: eth-mac-addr@FA {
            reg = <0xFA 0x06>;
        };
    };
};

&i2c2 {
	status = "okay";       
};

&mac0 {
	status = "okay";
	phy-mode = "sgmii";    
	nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";    
	/delete-property/ local-mac-address;    
	phy-handle = <&phy0>;
	phy0: ethernet-phy@1 {
		device-type = "ethernet-phy";
		reg = <1>;       
		reset-names = "ETH_RST";
		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};
};

&mac1 {
	status = "disabled";
};


&mbox {
	status = "okay";
};

&mmc {
	status = "okay";
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};


&qspi {
	status = "okay";
    num-cs = <1>;
};

&refclk {
	clock-frequency = <125000000>;
};


&spi0 {
	status = "okay";
};

&spi1 {
	status = "disabled";
};


&usb {
	status = "okay";
	dr_mode = "otg";  
    phys = <&usb_phy PHY_TYPE_USB2>;
};

 

Kernel

Start with Create a custom BSP layer for Intel SoC or FPGA#Configure linux kernel

File location: meta-<module>/recipes-kernel/linux/

Changes:

• No changes.

Images

Image recipe for minimal console image

File location: meta-<module>/recipes-images/yocto/

Image recipes:

• te-image-minimal.bb: create minimal linux image
• te-initramfs.bb: required for building an image with initial RAM Filesystem

Added packages/recipes:

• No packages/recipes

Rootfs

Used filesystem: Initial RAM Filesystem (initramfs)

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