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The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.
| GT Ref Clock LocationSelection | GT Clock(MHz) | Notes | |
|---|---|---|---|
| TE0712 | Quad_216 CLK0 | 125 | Si5338 Clock is connected to GT CLK2 input |
| TE0715 | Quad_112 CLK1 | 125 | Si5338 Clock is connected to GT CLK2 input |
| TE0741 | Quad_116 CLK1 | 125 | Si5338 Clock is connected to GT CLK1 input |
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