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The customizable IBERT core for 7 series FPGA can be used for evaluating and monitoring the GTs.

The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.

 

 Ref Clock SelectionGT Clock(MHz)Notes
TE0712216 CLK0125Si5338 Clock is connected to GT CLK2 input
TE0715112 CLK1125Si5338 Clock is connected to GT CLK2 input
TE0741116 CLK1125Si5338 Clock is connected to GT CLK1 input

 

Step to Step to generate the IBERT core:

  1. Create a new IP Location.


  2. Double-click IBERT 7 series GTP (or GTX).


  3. Define the new IBERT. Set the LineRate, select the DataWidth,  the Quad count,  the Refclk and the Clock Source.






  4. Generate the Core.




  5.  Right-click the IP in the Sources view, choose "Open IP Example Design".  



  6. A new project with the IBERT example design will be created and opened.


  7. Generate Bitstream. Open and view the completed design.


  8. Testing with Hardware

 

 

 

References

  1. LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTP Transceivers v3.0 (pg133)
  2. LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers v3.0 (pg132 )

 

 

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