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  • This line was added.
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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
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        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
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Notes :

Linux with basic periphery of TE0808 StarterKit (TEBF0808 Carrier).

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20212022.2.1
  • TEBF0808
  • PetaLinux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • Display Port (DP)
  • user LED access
  • Modified FSBL for Si5338 programming/ petalinux patch

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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DateVivadoProject BuiltAuthorsDescription
2023-09-142022.2TE0803-StarterKit-vivado_2022.2-build_8_20230914124643.zip
TE0803-StarterKit_noprebuilt-vivado_2022.2-build_8_20230914124643.zip
Manuela Strücker
  • 2022.2 update
  • new assembly variants
2022-10-172021.2.1TE0803-StarterKit-vivado_2021.2-build_18_20221017093105.zip
TE0803-StarterKit_noprebuilt-vivado_2021.2-build_18_20221017093105.zip
Manuela Strücker
  • script update
2022-08-302021.2.1TE0803-StarterKit-vivado_2021.2-build_15_20220830131524.zip
TE0803-StarterKit_noprebuilt-vivado_2021.2-build_15_20220830131524.zip
Manuela Strücker
  • new assembly variants
2022-04-052021.2TE0803-StarterKit-vivado_2021.2-build_11_20220405095407.zip
TE0803-StarterKit_noprebuilt-vivado_2021.2-build_11_20220405095407.zip
Manuela Strücker
  • 2021.2 update
2021-09-062020.2TE0803-StarterKit_noprebuilt-vivado_2020.2-build_7_20210906104631.zip
TE0803-StarterKit-vivado_2020.2-build_7_20210906104617.zip
Manuela Strücker
  • 2020.2 update
2020-04-062019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_9_20200406082458.zip
TE0803-StarterKit-vivado_2019.2-build_9_20200406082321.zip
John Hartfiel
  • new assembly variants
2020-03-252019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325082516.zip
TE0803-StarterKit-vivado_2019.2-build_8_20200325082450.zip
John Hartfiel
  • script update
2020-01-232019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_3_20200123065955.zip
TE0803-StarterKit-vivado_2019.2-build_3_20200123065933.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
2019-05-072018.3TE0803-StarterKit-vivado_2018.3-build_05_20190507093424.zip
TE0803-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507093443.zip
John Hartfiel
  • new assembly variant
  • TE Script update
  • rework of the FSBLs
  • SI5338 CLKBuilder Pro Project
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-10-252018.2TE0803-Starterkit-vivado_2018.2-build_03_20181026141553.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_03_20181026141611.zip
John Hartfiel
  • new assembly variant
2018-08-142018.2TE0803-Starterkit-vivado_2018.2-build_02_20180814103204.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip
John Hartfiel
  • new assembly variant
2018-07-232018.2TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip
John Hartfiel
  • correction on FSBL
2018-07-122018.2

TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip
TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip

John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-172017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip
TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip
John Hartfiel
  • new assembly variant
  • solved Linux flash issue
2018-04-112017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip
TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip
John Hartfiel
  • bugfix TE0803-01-04EG board part file
2018-02-132017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip
TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip
John Hartfiel
  • new assembly variant
2018-02-062017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip
TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip
John Hartfiel
  • same CLK for both VIO
2018-02-052017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip
TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip
John Hartfiel
  • new assembly variant
  • solved JTAG/Linux issue
2018-01-312017.4TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip
TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip
John Hartfiel
  • new assembly variant
2018-01-182017.4TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip
TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip
John Hartfiel
  • initial release



Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed

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IssuesDescriptionWorkaround/SolutionTo be fixed version
Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
MAC from EEPROM

The MAC address stored in the EEPROM is not read out and initialised correctly during start-up.
This is caused by two I2C expanders each switched to the same EEPROM with the same address
i2cswitch@73 --> i2c@5 --> reg = <0x50> and
i2cswitch@77 --> i2c@4 --> reg = <0x50>

Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.

Solved with 20220405update

QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
If flash programming fails, configure device for JTAG boot mode and try again or
use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
--
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180517 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Vitis20212022.2needed, Vivado is included into Vitis installation
PetaLinux20212022.2needed
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:


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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0803-01-02EG-1E2eg_2gbREV012GB64MBNANANA
TE0803-01-02CG-1E2cg_2gbREV012GB64MBNANANA
TE0803-01-03EG-1E3eg_2gbREV012GB64MBNANANA
TE0803-01-03CG-1E3cg_2gbREV012GB64MBNANANA
TE0803-01-02EG-1EA2eg_2gbREV012GB128MBNANANA
TE0803-01-02CG-1EA2cg_2gbREV012GB128MBNANANA
TE0803-01-03EG-1EA3eg_2gbREV012GB128MBNANANA
TE0803-01-03CG-1EA3cg_2gbREV012GB128MBNANANA
TE0803-02-03EG-1EB3eg_4gbREV02|REV014GB128MBNANANA
TE0803-01-04CG-1EA4cg_2gbREV012GB128MBNANANA
TE0803-02-04EV-1EA4ev_2gbREV02|REV012GB128MBNANANA
TE0803-01-04EV-1E34ev_2gbREV012GB128MBNA1 mm connectorsNA
TE0803-01-04EG-1EA4eg_2gbREV012GB128MBNANANA
TE0803-01-04CG-1EB4cg_2gbREV012GB256MBNANANA
TE0803-01-05EV-1EA5ev_2gbREV012GB128MBNANANA
TE0803-01-05EV-1IA5ev_i_2gbREV012GB128MBNANANA
TE0803-02-04EV-1E34ev_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-02-04EG-1E34eg_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-03-2AE11-A2cg_2gbREV032GB128MBNANANA
TE0803-03-2BE11-A2eg_2gbREV032GB128MBNANANA
TE0803-03-3AE11-A3cg_2gbREV032GB128MBNANANA
TE0803-03-3BE11-A3eg_2gbREV032GB128MBNANANA
TE0803-03-4AE11-A4cg_2gbREV032GB128MBNANANA
TE0803-03-4BE11-A4eg_2gbREV032GB128MBNANANA
TE0803-03-4BE21-L4eg_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4BI21-A4eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DE11-A4ev_2gbREV032GB128MBNANANA
TE0803-03-4DE21-L4ev_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GE21-L4eg_2_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-5DE11-A5ev_2gbREV032GB128MBNANANA
TE0803-03-5DI21-A5ev_i_4gbREV034GB128MBNANANA
TE0803-03-3RI21-A3eg_li_4gbREV034GB128MBNANANA
TE0803-03-3BI21-A3eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DI21-L4ev_i_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GI11-A4eg_2i_2gbREV032GB128MBNANANA
TE0803-03-4GE11-A4eg_2_2gbREV032GB128MBNANANA
TE0803-03-4GI21-A4eg_2i_4gbREV034GB128MBNANANA
TE0803-03-5BE11-A5eg_2gbREV032GB128MBNANANA
TE0803-03-5DI24-A5ev_i_4gbREV034GB512MBNANANA
TE0803-03-4BI21-X4eg_i_4gbREV034GB128MBNANAU41 replaced with diode
TE0803-03-3BE21-A3eg_4gbREV034GB128MBNANANA
TE0803-03-3BE31-A*3eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-2AE11-A2cg_2gbREV042GB128MBNANANA
TE0803-04-2BE11-A2eg_2gbREV042GB128MBNANANA
TE0803-04-3AE11-A3cg_2gbREV042GB128MBNANANA
TE0803-04-3BE11-A3eg_2gbREV042GB128MBNANANA
TE0803-04-4BE21-L4eg_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4BI21-A4eg_i_4gbREV044GB128MBNANANA
TE0803-04-4BI21-X4eg_i_4gbREV044GB128MBNANAU41 replaced with diode
TE0803-03-4BI61-A4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-03-4BI61-X4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-4BI61-A4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4BI61-X4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4DE11-A4ev_2gbREV042GB128MBNANANA
TE0803-04-4DE21-L4ev_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4DI21-L4ev_i_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-03-4DI21-D4ev_i_4gbREV034GB128MBNANANA
TE0803-04-4DI21-D4ev_i_4gbREV044GB128MBNANANA
TE0803-04-4GE21-L4eg_2_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4GI21-A4eg_2i_4gbREV044GB128MBNANANA
TE0803-04-5BE11-A5eg_2gbREV042GB128MBNANANA
TE0803-04-5DE11-A5ev_2gbREV042GB128MBNANANA
TE0803-04-5DI21-A5ev_i_4gbREV044GB128MBNANANA
TE0803-03-S0034ev_2gbREV042GB128MBNANACAO
TE0803-03-S0064ev_4gbREV044GB128MBNA1 mm connectorsCAO
TE0803-04-4BE11-A4eg_2gbREV042GB128MBNANACAO
TE0803-03-S0054eg_2gbREV032GB128MBNANACAO: TE0803-03-4BI1?-A
TE0803-04-S0094eg_2_4gbREV044GB128MBNA1 mm connectorsCAO: TE0803-04-4GE21-L
TE0803-04-S0114eg_2_4gbREV044GB64MBNA1 mm connectorsCAO: TE0803-04-4GE25-L
TE0803-04-4AE11-A4cg_2gbREV042GB128MBNANANA
TE0803-04-S0122cg_2gbREV042GB128MBNANACAO
*used as reference

Note: Design contains also Board Part Files for TE0803 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

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Carrier ModelNotesTEBF0808*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

*used as reference

Additional HW Requirements:

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Additional HardwareNotesDP Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL P2421

USB KeyboardOptional HW
Can be used to get access to console which is show on DPUSB StickOptional HW
USB was tested with USB memory stickSATA DiskOptional HWPCIe CardOptional HWETH cableOptional HW
Ethernet works with DHCP, but can be setup also manuallySD cardwith fat32 partition

Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

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TypeLocationNotesVivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_filesVivado Project will be generated by TE ScriptsVitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generationPetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
TE0803-03-4DE21-LZ4ev_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-3AE11-AK3cg_2gbREV032GB128MBNANANA
TE0803-04-4AE11-AK4cg_2gbREV042GB128MBNANANA
TE0803-04-4DE11-AZ4ev_2gbREV042GB128MBNANANA
TE0803-04-S0133cg_2gbREV042GB128MBNANANA
TE0803-04-S0144eg_2_4gbREV044GB64MBNA1 mm connectorsCAO: TE0803-04-4GE2?-LZ
TE0803-04-S0164cg_2gbREV042GB128MBNANANA
TE0803-04-S0172eg_2gbREV042GB128MBNANANA
TE0803-04-S0184eg_2_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-S0204cg_2gbREV042GB128MBNANANA
TE0803-04-3BE21-L3eg_4gbREV044GB128MBNANANA
TE0803-04-4AE11-AZ4cg_2gbREV042GB128MBNANANA
TE0803-04-4DE21-LZ4ev_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-3AE11-AK3cg_2gbREV042GB128MBNANANA
TE0803-04-S0224eg_2_4gbREV044GB128MBNA1 mm connectorsCAO: TE0803-04-4GE21-LZ
TE0803-04-S0234eg_2_4gbREV044GB128MBNA1 mm connectorsCAO: TE0803-04-4GE81-L
TE0803-04-4BE11-AK4eg_2gbREV042GB128MBNANANA
TE0803-04-S0265ev_i_4gbREV044GB128MBNANACAO: TE0803-04-5DI21-A
TE0803-04-2BE11-AK2eg_2gbREV042GB128MBNANANA
TE0803-04-S0105ev_2gbREV042GB128MBNANACAO: TE0803-04-5DE11-A

*used as reference

Note: Design contains also Board Part Files for TE0803 only configuration, this board part files are not used for this reference design.

Design supports following carriers

Additional Sources

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TypeLocationNotesSI5338<project folder>\misc\PLL\Si5338_BSI5338 Project with current PLL Configurationinit.sh<project folder>\misc\sdAdditional Initialization Script for Linux

Prebuilt

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  • prebuilt files
  • Template Table

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    PFPrebuilt files
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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

    Debian SD-Image

    *.img

    Debian Image for SD-Card

    Diverse Reports---Report files in different formats
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File

    MCS-File

    *.mcs

    Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

    MMI-File

    *.mmi

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    SREC-File

    *.srec

    Converted Software Application for MicroBlaze Processor Systems

    Carrier ModelNotes
    TEBF0808*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

    *used as reference

    Additional HW Requirements:

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    Additional HardwareNotes
    DP Monitor

    Optional HW
    Not all monitors are supported, also Adapter to other Standard can make trouble.
    Design was tested with DELL P2421

    USB KeyboardOptional HW
    Can be used to get access to console which is show on DP
    USB StickOptional HW
    USB was tested with USB memory stick
    SATA DiskOptional HW
    PCIe CardOptional HW
    ETH cableOptional HW
    Ethernet works with DHCP, but can be setup also manually
    SD cardwith fat32 partition


    Content

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    Notes :

    • content of the zip file

    For general structure and usage of the reference design, see Project Delivery - AMD devices

    Design Sources

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    FileTypeFile-ExtensionLocation

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
    Notes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files
    Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



    Additional Sources

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    TypeLocationNotes
    SI5338<project folder>\misc\PLL\Si5338_BSI5338 Project with current PLL Configuration
    init.sh<project folder>\misc\sdAdditional Initialization Script for Linux



    Prebuilt

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    Design Flow

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    Notes :

    • prebuilt files
    • Template Table:

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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





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    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
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      title_create_win_setup.cmd/_create_linux_setup.sh
      --
    Page properties
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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
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      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      ----------------------Set design paths-------------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      ----------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide)
    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    4. ----------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide)


    5. Press 0 and enter to start "Module Selection Guide"
    6. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        • Important: Use Board Part Files, which ends with *_tebf0808


    7. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    8. optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow

      • Important: Use Board Part Files, which ends with *_tebf0808

      Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
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      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt
      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.

    9. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    10. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    11. Copy PetaLinux build image files to prebuilt folder

      copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      Info

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ...

      • ...

      Generate Programming Files with Vitis

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      titlerun on Vivado TCL (Script generates applications design and bootable files, which are defined in "test_board\sw_lib\apps_list.csvexport files into "<project folder>\prebuilt\hardware\<short name>")
      TE::swhw_runbuild_vitisdesign -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

    Launch

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    1. export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    2. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    3. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    4. Generate Programming Files with Vitis (recommended)
      1. Copy PetaLinux build image files to prebuilt folder
        • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          Info

          "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

  • Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  • Press 0 and enter to start "Module Selection Guide"
  • Select assembly version
  • Validate selection
  • Select create and open delivery binary folder

    Info

    Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash.

  • Connect JTAG and power on carrier with module
  • Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0803
  • Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  • Set Boot Mode to QSPI-Boot
    • Depends on Carrier, see carrier TRM.
    • TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
  • SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

  • Prepare HW like described on section Programming
  • Connect UART USB (JTAG XMOD)
  • Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.

    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  • (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  • (Optional with TEBF0808) Connect SATA Disc
  • (Optional with TEBF0808) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  • (Optional with TEBF0808) Connect Network Cable
  • Power On PCB

    Expand
    titleboot process

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

    Linux

    Open Serial Console (e.g. putty)
  • Speed: 115200
  • select COM Port

    Info

    Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

    Linux Console:

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    # password default disabled with 2021.2 petalinux release
    petalinux login: root
    Password: root
    Info

    Note: Wait until Linux boot finished

    You can use Linux shell now.

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    i2cdetect -y -r 0	(check I2C Bus, replace 0 with other bus number is also possible)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
    lspci				(PCIe check)
        • This step depends on Xilinx Device/Hardware

          for Zynq-7000 series

          • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for ZynqMP

          • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for Microblaze

          • ...


      1. Generate Programming Files with Vitis
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        titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
        TE::sw_run_vitis -all
        TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


        Note

        TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


    1. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp hello_te0803


    3. Copy image.ub and boot.scr on SD or USB
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    4. Set Boot Mode to QSPI-Boot
      • Depends on Carrier, see carrier TRM.
      • TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area


    SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (JTAG XMOD)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional with TEBF0808) Connect SATA Disc
    6. (Optional with TEBF0808) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional with TEBF0808) Connect Network Cable
    8. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • select COM Port

        Info

        Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


    2. Linux Console:

      Code Block
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      # password disabled
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished


    3. You can use Linux shell now.

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      i2cdetect -y -r 0	(check I2C Bus, replace 0 with other bus number is also possible)
      dmesg | grep rtc	(RTC check)
      udhcpc				(ETH0 check)
      lsusb				(USB check)
      lspci				(PCIe check)


    4. Option Features

      • Webserver to get access to Zynq
        • insert IP on web browser to start web interface
      • init.sh scripts
        • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

    Vivado Hardware Manager

  • Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
  • Vivado Hardware Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...
    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    Control:LEDs: XMOD 2 (without green dot) and HD LED are accessible.
  • CAN_S
  • Scroll Title
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    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    Scroll Title
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    titlePS Interfaces
    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...
    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    • Control:
      • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
      • CAN_S
    Scroll Title
    anchorFigure_VHM
    title-alignmentcenter
    titleVivado Hardware Manager


    Image Added

    Image Added


    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    titleBlock Design


    Image Added


    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    Scroll Title
    anchorTable_PSI
    title-alignmentcenter
    titlePS Interfaces

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeNote
    DDR
    QSPIMIO
    SD0MIO
    SD1MIO
    CAN0EMIO
    I2C0MIO
    PJTAG0MIO
    UART0MIO
    GPIO0MIO
    SWDT0..1
    TTC0..3
    GEM3MIO
    USB0MIO/GTP
    PCIeMIO/GTP
    SATAGTP
    DisplayPortEMIO/GTP



    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_io.xdc
    # system controller ip
    #LED_HD SC0 J3:31
    #LED_XMOD SC17 J3:48 
    #CAN RX SC19 J3:52 B26_L11_P
    #CAN TX SC18 J3:

    Scroll Table Layout
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    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeNoteDDRQSPIMIOSD0MIOSD1MIOCAN0EMIOI2C0MIOPJTAG0MIOUART0MIOGPIO0MIOSWDT0..1TTC0..3GEM3MIOUSB0MIO/GTPPCIeMIO/GTPSATAGTPDisplayPortEMIO/GTP

    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_io.xdc
    # system controller ip
    #LED_HD SC0 J3:31
    #LED_XMOD SC17 J3:48 
    #CAN RX SC19 J3:52 B26_L11_P
    #CAN TX SC18 J3:50 B26_L11_N
    #CAN S  SC16 J3:46 B26_L1_N
    
    set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
    set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
    set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
    set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
    set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
    set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
    set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
    set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
    set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
    set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
    set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
    set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
    set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
    set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
    
    # Audio Codec
    #LRCLK		 J3:49 
    #BCLK		 J3:51 
    #DAC_SDATA	 J3:53 
    #ADC_SDATA	 J3:55 
    set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ]
    set_property PACKAGE_PIN L14 [get_ports I2S_bclk ]
    set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
    set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]   

    Software Design - Vitis

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    # MGTs only for ZU4/5 Devices
    #   Y6    MGT_224_CLK0_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> floating
    #   Y5    MGT_224_CLK0_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> floating
    #   V6    MGT_224_CLK1_P -> U5,38 -> Si5338 -> CLK1
    #   V5    MGT_224_CLK1_N -> U5,37 -> Si5338 -> CLK1
    
    #set_property PACKAGE_PIN Y6   [get_ports {MGT_CLK_IN_clk_p[0]}]
    #set_property PACKAGE_PIN V6   [get_ports {MGT_CLK_IN_clk_p[1]}]  

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis


    Application

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    Page properties
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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 2021.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 2021.2 xilisf_v5_11

    Changed default Flash type to 5.
    Page properties
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    ----------------------------------------------------------

    Zynq FPGA Example:

    fsbl

    TE modified 2021.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 2022.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 2022.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 2021.2 FSBL

    General:

    Zynq Example:

    ----------------------------------------------------------

    fsbl

    TE modified 2022.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooksModified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_

      xfsbl

      fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device NameID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY


    ----------------------------------------------------------

    ZynqMP Example:Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 2021.2 FSBL

    General:

    Modified Files: xfsbl_main.c, xfsbl_

    zynqmp_fsbl

    TE modified 2022.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG
    +PCIe
      • Reset over MIO
  • I2C MUX for EEPROM MAC
  • zynqmp_

    fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    hello_te0803

    Hello TE0803

    pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    ----------------------------------------------------------

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Software Design -  PetaLinux

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 2022.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • OTG+PCIe Reset over MIO
      • I2C MUX for EEPROM MAC

    hello_te0803

    Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and  project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Changes:

    adjust Ethernet MAC Address (not necessary with the next version)

      • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
      select SD default instead of eMMC:
      • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
      generate u-boot.dtb:
    • add new flash partition for bootscr and sizing
      • CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
      add new flash partition for bootscr and sizing
      • FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0PART1_SIZE=0xA000000x2000000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x20000000x40000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
    • Identification
      • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
      • CONFIG_SUBSYSTEM_PRODUCT="TE0803_TEBF0808"

    U-Boot

    Start with petalinux-config -c u-boot
    Changes:

    • MAC from eeprom together with uboot and device tree settings:
      • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFACONFIG_ENV_OVERWRITE=y
      • CONFIG_ZYNQ_SYSMAC_I2CIN_EEPROM _ADDR=0x50is not set
      • CONFIG_SYSNET_I2C_EEPROM_BUS=7RANDOM_ETHADDR is not set
    • Boot Modes:
      • CONFIG_QSPI_BOOT=y
      • CONFIG_SD_BOOT=y
      • CONFIG_ENV_IS_IN_FAT is not set
      • # CONFIG_ENV_IS_IN_NAND is not set
      • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000

    Change platform-top.h:

    Code Block
    languagejs
    #no changes

    Device Tree

    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    / {
      chosen {
        xlnx,eeprom = &eeprom;
      };
    };
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <27000000>;
      };
       
       refclk2:psgtr_pcie_usb_clock {
               compatible = "fixed-clock";
               #clock-cells = <0x00>;
               clock-frequency = <100000000>;
       };
        
      //refclk1:psgtr_unused_clock {
      //        compatible = "fixed-clock";
      //        #clock-cells = <0x00>;
      //        clock-frequency = <100000000>;
      //};
        
      refclk0:psgtr_sata_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <150000000>;
      };
    };
     
    &psgtr {
      clocks = <&refclk0 &refclk2 &refclk3>;
      /* ref clk instances used per lane */
      clock-names = "ref0\0ref2\0ref3";
    };
    /*------------------ SD --------------------*/
    &sdhci0 {
        // disable-wp;
        no-1-8-v;
     
    };
     
    &sdhci1 {
        // disable-wp;
        no-1-8-v;
     
    };
     
     
    /*------------------ USB --------------------*/
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy";
        maximum-speed = "super-speed";
    };
    
    
    /*------------------ ETH PHY --------------------*/
    &gem3 {
        phy-handle = <&phy0>;
        phy0: phy0@1 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
     
    /*------------------ QSPI --------------------*/
    &qspi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73>;
            i2c-mux-idle-disconnect;
            i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // SFP TEBF0808 PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
            };
            i2c@2 { // PCIe
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // SFP1 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 {// SFP2 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { // TEBF0808 EEPROM
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
                eeprom: eeprom@50 {
                    compatible = "atmel,24c08";
                    reg = <0x50>;
                  };
            };
            i2c@6 { // TEBF0808 FMC 
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 USB HUB
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
        i2cswitch@77 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x77>;
            i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0808 PMOD P1
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // i2c Audio Codec
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
                /*
                adau1761: adau1761@38 {
                    compatible = "adi,adau1761";
                    reg = <0x38>;
                };
                */
            };
            i2c@2 { // TEBF0808 Firefly A
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // TEBF0808 Firefly B
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 { //Module PLL Si5338 or SI5345
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { //TEBF0808 CPLD
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
            };
            i2c@6 { //TEBF0808 Firefly PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 PMOD P3
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
    };
     
     
     
      • ENV_IS_IN_SPI_FLASH is not set
      • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
      • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
    • Identification
      • CONFIG_IDENT_STRING=" TE0803_TEBF0808"


    Change platform-top.h:

    Code Block
    languagejs
    #no changes

    Device Tree

    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
    
    / {
      refclk3:psgtr_dp
    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\uboot-device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    / {
      chosen {
        xlnx,eeprom = &eeprom;
      };
    };
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <27000000>;
      };
       
       refclk2:psgtr_pcie_usb_clock {
               compatible = "fixed-clock";
               #clock-cells = <0x00>;
               clock-frequency = <100000000>;
       };
        
      //refclk1:psgtr_unused_clock {
      //        compatible = "fixed-clock";
      //        #clock-cells = <0x00>;
      //        clock-frequency = <100000000>;
      //};
        
      refclk0:psgtr_sata_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <150000000><27000000>;
      };
    };
      
    &psgtr {
      clocks = <&refclk0 &refclk2 &refclk3>;refclk2:psgtr_pcie_usb_clock {
      /* ref clk instances used per lane */
      clock-namescompatible = "ref0\0ref2\0ref3";
    };
    /*------------------ SD --------------------*/
    &sdhci0 {
    fixed-clock";
           // disable-wp;
      #clock-cells  no-1-8-v= <0x00>;
     
    };
     
    &sdhci1 {
        // disable-wp;
      clock-frequency  no-1-8-v= <100000000>;
      
    };
     
     
    /*------------------ USB --------------------*/
    &dwc3_0 {
     //refclk1:psgtr_unused_clock {
      //        statuscompatible = "okayfixed-clock";
      //  dr_mode      #clock-cells = "host"<0x00>;
      //      snps,usb3_lpm_capable;
      clock-frequency  snps,dis_u3_susphy_quirk= <100000000>;
      //};
    
      snps,dis_u2_susphy_quirk;refclk0:psgtr_sata_clock {
        phy-names = "usb2-phy","usb3-phy";
        maximum-speedcompatible = "superfixed-speedclock";
    };
    
    
    /*------------------ ETH PHY --------------------*/
    &gem3 {
              phy#clock-handlecells = <&phy0><0x00>;
           phy0: phy0@1 {
     clock-frequency = <150000000>;
      };
    };
    
    &psgtr {
      device_typeclocks = "ethernet-phy" <&refclk0 &refclk2 &refclk3>;
      /* ref clk instances used per reg = <1>;lane */
      clock-names  }= "ref0\0ref2\0ref3";
    };
    
    
     
    /*------------------ QSPISD --------------------*/
    &qspisdhci0 {
        #address-cells = <1>// disable-wp;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>no-1-8-v;
    
    };
    
    &sdhci1 {
        // disable-wp;
        }no-1-8-v;
    
    };
    
    
    /*------------------- I2CUSB --------------------*/
    &i2c0dwc3_0 {
        i2cswitch@73status { // u= "okay";
            compatible dr_mode = "nxp,pca9548host";
            #address-cells = <1>snps,usb3_lpm_capable;
            #size-cells = <0>snps,dis_u3_susphy_quirk;
            reg = <0x73>snps,dis_u2_susphy_quirk;
        phy-names =   i2c-mux-idle-disconnect"usb2-phy","usb3-phy";
        maximum-speed = "super-speed";
    };
    
    
    /*------------------ ETH i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembledPHY --------------------*/
    &gem3 {
        /delete-property/ local-mac-address;
           #address-cellsphy-handle = <1><&phy0>;
        
            #sizenvmem-cells = <0><&eth0_addr>;
        nvmem-cell-names      = "mac-address";
      reg = <0>;
        phy0: phy0@1 {
      };
          device_type  i2c@1 { // SFP TEBF0808 PCF8574DWR
    = "ethernet-phy";
            reg = <1>;
        };
    };
     
    /*----------------- SATA  #address-cells = <1>;PHY --------------------*/
    &sata {
     
                #size-cellsceva,p0-burst-params = <0><0x13084a06>;
                regceva,p0-cominit-params = <1><0x18401828>;
            };
            i2c@2 { // PCIeceva,p0-comwake-params = <0x614080e>;
                #address-cellsceva,p0-retry-params = <1><0x96a43ffc>;
                #size-cellsceva,p1-burst-params = <0><0x13084a06>;
                regceva,p1-cominit-params = <2><0x18401828>;
            }    ceva,p1-comwake-params = <0x614080e>;
            i2c@3 { // SFP1 TEBF0808
             ceva,p1-retry-params = <0x96a43ffc>;
     
    };
     
     
    /*-------------------- QSPI ---------------------*/
    &qspi {
        #address-cells = <1>;
                #size-cells = <0>;
        status = "okay";
        flash0: flash@0 reg{
     = <3>;
          compatible  }= "jedec,spi-nor";
            i2c@4reg {// SFP2 TEBF0808= <0x0>;
                #address-cells = <1>;
                #size-cells = <0><1>;
                reg = <4>;
            };
            i2c@5};
    };
    
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 { // u
         TEBF0808 EEPROM
      compatible = "nxp,pca9548";
            #address-cells = <1>;
                #size-cells = <0>;
                reg = <5><0x73>;
            i2c-mux-idle-disconnect;
           eeprom: eeprom@50i2c@0 {
     // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                compatiblereg = "atmel,24c08"<0>;
            };
            i2c@1 { // regSFP =TEBF0808 <0x50>;PCF8574DWR
                reg = }<1>;
            };
            i2c@6i2c@2 { // TEBF0808 FMC PCIe
                #address-cellsreg = <1><2>;
            };
            i2c@3 { #size-cells = <0>;// SFP1 TEBF0808
                reg = <6><3>;
            };
            i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB
    
                reg = <4>;
           #address-cells = <1> };
            i2c@5 { //  #size-cells = <0>;TEBF0808 EEPROM
                reg = <7><5>;
              };
      eeprom: eeprom@50 };{
        i2cswitch@77  { // u
            compatible = "nxpmicrochip,pca954824aa025";
            #address-cells = <1>, "atmel,24c02";
            #size-cells = <0>;
            reg = <0x77><0x50>;
            i2c-mux-idle-disconnect;
            i2c@0 {
     // TEBF0808 PMOD P1
                #address-cells = <1>;
                    #size-cells = <0><1>;
                reg = <0>;
      eth0_addr:      };
            i2c@1 { // i2c Audio Codec
    eth-mac-addr@FA {
                      #address-cellsreg = <0xFA <1>0x06>;
                  #size-cells = <0>};
                reg = <1>};
            };
            i2c@6 { // TEBF0808 /*FMC
                adau1761:reg adau1761@38= {<6>;
            };
            compatiblei2c@7 = "adi,adau1761";
       { // TEBF0808 USB HUB
                 reg = <0x38><7>;
            };
        };
        i2cswitch@77 { // u
         */
       compatible     }= "nxp,pca9548";
            i2c@2reg { // TEBF0808 Firefly A= <0x77>;
                #address-cells = <1>i2c-mux-idle-disconnect;
            i2c@0 {   #size-cells = <0>;// TEBF0808 PMOD P1
                reg = <2><0>;
            };
            i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec
                #address-cellsreg = <1>;
                #size-cells = <0>;/*
                regadau1761: =adau1761@38 <3>;{
            };
            i2c@4compatible { //Module PLL Si5338 or SI5345
    = "adi,adau1761";
                    #address-cellsreg = <1><0x38>;
                #size-cells = <0>};
                reg = <4>;*/
            };
            i2c@5i2c@2 { // TEBF0808 Firefly CPLDA
                #address-cellsreg = <1><2>;
            };
            #size-cells = <0>;i2c@3 { // TEBF0808 Firefly B
                reg = <5><3>;
            };
            i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345
                #address-cellsreg = <1><4>;
            };
        #size-cells = <0>;    i2c@5 { //TEBF0808 CPLD
                reg = <6><5>;
            };
            i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR
                #address-cellsreg = <1><6>;
            };
             #size-cells = <0>;i2c@7 { // TEBF0808 PMOD P3
                reg = <7>;
            };
        };
    };
     
     
     

    FSBL patch

    Must be add manually, see template

     

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    • Only needed to fix JTAG Debug issue:
      • # CONFIG_CPU_IDLE is not set# CONFIG_CPU_FREQ is not setCONFIG_EDAC_CORTEX_ARM64=y
    • Support PCIe memory card
      • CONFIG_NVME_CORE=y
      • CONFIG_BLK_DEV_NVME=y
      • # CONFIG_NVME_MULTIPATH is not set
      • # CONFIG_NVME_HWMON is not set#
      • CONFIG_NVME_TCP is not setCONFIG_NVME_TARGET=y
      • # CONFIG_NVME_TARGET_PASSTHRU is not set
      • # CONFIG_NVME_TARGET_LOOP is not set
      • # CONFIG_NVME_TARGET_FC is not set
      • # CONFIG_NVME_TARGET_TCP is not set
      • CONFIG_SATA_AHCI=y
      • CONFIG_SATA_MOBILE_LPM_POLICY=0
      • CONFIG_NVM=y
      • CONFIG_NVM_PBLK=y
      • CONFIG_NVM_PBLK_DEBUG=y

    Rootfs

    Start with petalinux-config -c rootfs

    Changes:

    • For web server app:
      • CONFIG_busybox-httpd=y
    • For additional test tools only:
      • CONFIG_i2c-tools=y
      • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
      • CONFIG_i2c-tools=y
      • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
    • For auto login:
      • CONFIG_auto-login=y
      • CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"

    FSBL patch (alternative for vitis fsbl trenz patch)

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

    Note

    te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"

    Applications

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

    startup

    Script App to load init.sh from SD Card if available.

    webfwu

    Webserver application suitable for Zynq access. Need busybox-httpd

    Additional Software

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    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:

    SI5338

    File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"

    General documentation how you work with this project will be available on Si5338


    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Release 2022.2
    • new assembly variants
    2022-10-17v.36Manuela Strücker
    • script update
    2022-09-06v.35Manuela Strücker
    • new assembly variants
    2022-07-15v.33Manuela Strücker
    • Release 2021.2
    2021-09-09v.29Manuela Strücker
    • Release 2020.2
    • update document style
    2020-04-06v.28John Hartfiel
    • new assembly variants
    2020-03-25v.27John Hartfiel
    • script update
    2020-02-25v.26John Hartfiel
    • Update requirement section
    2020-01-23v.25John Hartfiel
    • Release 2019.2
    2019-05-07v.24John Hartfiel
    • Release 2018.3
    2018-10-26v.21John Hartfiel
    • new assembly variant

    2018-08-14

    v.19John Hartfiel
    • design update

    2018-07-23

    v.18John Hartfiel
    • new assembly variant

    2018-07-20

    v.16John Hartfiel
    • Release 2018.2

    2018-05-17

    v.14

    John Hartfiel
    • new assembly variant
    • solved known issues

    2018-04-30

    v.13John Hartfiel
    • Update known Issues

    2018-04-11

    v.12John Hartfiel
    • bugfix board part files

    2018-02-13

    v.11John Hartfiel
    • new assembly variant
    • solved known issues
    2018-01-29v.4John Hartfiel
    • Update known Issues
    2018-01-18v.3John Hartfiel
    • Release 2017.4

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