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Overview


Linux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2
  • TEBF0808
  • PetaLinux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • Display Port (DP)
  • user LED access
  • Modified FSBL for Si5338 programming/ petalinux patch
  • Special FSBL for QSPI Programming

Revision History

DateVivadoProject BuiltAuthorsDescription
2021-09-062020.2TE0803-StarterKit_noprebuilt-vivado_2020.2-build_7_20210906104631.zip
TE0803-StarterKit-vivado_2020.2-build_7_20210906104617.zip
Manuela Strücker
  • 2020.2 update
2020-04-062019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_9_20200406082458.zip
TE0803-StarterKit-vivado_2019.2-build_9_20200406082321.zip
John Hartfiel
  • new assembly variants
2020-03-252019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325082516.zip
TE0803-StarterKit-vivado_2019.2-build_8_20200325082450.zip
John Hartfiel
  • script update
2020-01-232019.2TE0803-StarterKit_noprebuilt-vivado_2019.2-build_3_20200123065955.zip
TE0803-StarterKit-vivado_2019.2-build_3_20200123065933.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
2019-05-072018.3TE0803-StarterKit-vivado_2018.3-build_05_20190507093424.zip
TE0803-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507093443.zip
John Hartfiel
  • new assembly variant
  • TE Script update
  • rework of the FSBLs
  • SI5338 CLKBuilder Pro Project
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-10-252018.2TE0803-Starterkit-vivado_2018.2-build_03_20181026141553.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_03_20181026141611.zip
John Hartfiel
  • new assembly variant
2018-08-142018.2TE0803-Starterkit-vivado_2018.2-build_02_20180814103204.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip
John Hartfiel
  • new assembly variant
2018-07-232018.2TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip
John Hartfiel
  • correction on FSBL
2018-07-122018.2

TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip
TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip

John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-172017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip
TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip
John Hartfiel
  • new assembly variant
  • solved Linux flash issue
2018-04-112017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip
TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip
John Hartfiel
  • bugfix TE0803-01-04EG board part file
2018-02-132017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip
TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip
John Hartfiel
  • new assembly variant
2018-02-062017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip
TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip
John Hartfiel
  • same CLK for both VIO
2018-02-052017.4TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip
TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip
John Hartfiel
  • new assembly variant
  • solved JTAG/Linux issue
2018-01-312017.4TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip
TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip
John Hartfiel
  • new assembly variant
2018-01-182017.4TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip
TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues


IssuesDescriptionWorkaround/SolutionTo be fixed version
QSPI FlashProgramming QSPI flash fails sometimesuse Vivado 2019.2 for programming
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180517 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update
Known Issues

Requirements

Software

SoftwareVersionNote
Vitis2020.2needed, Vivado is included into Vitis installation
PetaLinux2020.2needed
SI ClockBuilder Pro---optional
Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0803-01-02EG-1E2eg_2gbREV012GB64MBNANANA
TE0803-01-02CG-1E2cg_2gbREV012GB64MBNANANA
TE0803-01-03EG-1E3eg_2gbREV012GB64MBNANANA
TE0803-01-03CG-1E3cg_2gbREV012GB64MBNANANA
TE0803-01-02EG-1EA2eg_2gbREV012GB128MBNANANA
TE0803-01-02CG-1EA2cg_2gbREV012GB128MBNANANA
TE0803-01-03EG-1EA3eg_2gbREV012GB128MBNANANA
TE0803-01-03CG-1EA3cg_2gbREV012GB128MBNANANA
TE0803-02-03EG-1EB3eg_4gbREV02|REV014GB128MBNANANA
TE0803-01-04CG-1EA4cg_2gbREV012GB128MBNANANA
TE0803-02-04EV-1EA4ev_2gbREV02|REV012GB128MBNANANA
TE0803-01-04EV-1E34ev_2gbREV012GB128MBNA1 mm connectorsNA
TE0803-01-04EG-1EA4eg_2gbREV012GB128MBNANANA
TE0803-01-04CG-1EB4cg_2gbREV012GB256MBNANANA
TE0803-01-05EV-1EA5ev_2gbREV012GB128MBNANANA
TE0803-01-05EV-1IA5ev_i_2gbREV012GB128MBNANANA
TE0803-02-04EV-1E34ev_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-02-04EG-1E34eg_4gbREV024GB128MBNA1 mm connectorsNA
TE0803-03-2AE11-A2cg_2gbREV032GB128MBNANANA
TE0803-03-2BE11-A2eg_2gbREV032GB128MBNANANA
TE0803-03-3AE11-A3cg_2gbREV032GB128MBNANANA
TE0803-03-3BE11-A3eg_2gbREV032GB128MBNANANA
TE0803-03-4AE11-A4cg_2gbREV032GB128MBNANANA
TE0803-03-4BE11-A4eg_2gbREV032GB128MBNANANA
TE0803-03-4BE21-L4eg_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4BI21-A4eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DE11-A4ev_2gbREV032GB128MBNANANA
TE0803-03-4DE21-L4ev_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GE21-L4eg_2_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-5DE11-A5ev_2gbREV032GB128MBNANANA
TE0803-03-5DI21-A5ev_i_4gbREV034GB128MBNANANA
TE0803-03-3RI21-A3eg_li_4gbREV034GB128MBNANANA
TE0803-03-3BI21-A3eg_i_4gbREV034GB128MBNANANA
TE0803-03-4DI21-L4ev_i_4gbREV034GB128MBNA1 mm connectorsNA
TE0803-03-4GI11-A4eg_2i_2gbREV032GB128MBNANANA
TE0803-03-4GE11-A4eg_2_2gbREV032GB128MBNANANA
TE0803-03-4GI21-A4eg_2i_4gbREV034GB128MBNANANA
TE0803-03-5BE11-A5eg_2gbREV032GB128MBNANANA
TE0803-03-5DI24-A5ev_i_4gbREV034GB512MBNANANA
TE0803-03-4BI21-X4eg_i_4gbREV034GB128MBNANAU41 replaced with diode
TE0803-03-3BE21-A3eg_4gbREV034GB128MBNANANA
TE0803-03-3BE31-A*3eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-2AE11-A2cg_2gbREV042GB128MBNANANA
TE0803-04-2BE11-A2eg_2gbREV042GB128MBNANANA
TE0803-04-3AE11-A3cg_2gbREV042GB128MBNANANA
TE0803-04-3BE11-A3eg_2gbREV042GB128MBNANANA
TE0803-04-4BE21-L4eg_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4BI21-A4eg_i_4gbREV044GB128MBNANANA
TE0803-04-4BI21-X4eg_i_4gbREV044GB128MBNANAU41 replaced with diode
TE0803-03-4BI61-A4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-03-4BI61-X4eg_8gbREV038GB128MBNANAdual die ddr
TE0803-04-4BI61-A4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4BI61-X4eg_8gbREV048GB128MBNANAdual die ddr
TE0803-04-4DE11-A4ev_2gbREV042GB128MBNANANA
TE0803-04-4DE21-L4ev_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4DI21-L4ev_i_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-03-4DI21-D4ev_i_4gbREV034GB128MBNA
NA
TE0803-04-4DI21-D4ev_i_4gbREV044GB128MBNA
NA
TE0803-04-4GE21-L4eg_2_4gbREV044GB128MBNA1 mm connectorsNA
TE0803-04-4GI21-A4eg_2i_4gbREV044GB128MBNANANA
TE0803-04-5BE11-A5eg_2gbREV042GB128MBNANANA
TE0803-04-5DE11-A5ev_2gbREV042GB128MBNANANA
TE0803-04-5DI21-A5ev_i_4gbREV044GB128MBNANANA

*used as reference

Hardware Modules

Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Carrier ModelNotes
TEBF0808*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
DP Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL P2421

USB KeyboardOptional HW
Can be used to get access to console which is show on DP
USB StickOptional HW
USB was tested with USB memory stick
Sata DiskOptional HW
PCIe CardOptional HW
ETH cableOptional HW
Ethernet works with DHCP, but can be setup also manually
SD cardwith fat32 partition
Additional Hardware

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes
SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
init.sh<project folder>\misc\sdAdditional Initialization Script for Linux
Additional design sources

Prebuilt


File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Source*.scr

Distro Boot file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.


Reference Design is available on:

Design Flow


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    _create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide)
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

      • Important: Use Board Part Files, which ends with *_tebf0808
  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  8. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch


Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0803 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.
    • TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area


SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (JTAG XMOD)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  5. (Optional) Connect SATA Disc
  6. (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  7. (Optional) Connect Network Cable
  8. Power On PCB

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
    lspci				(PCIe check)
  4. Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado Hardware Manager


Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

  • Control:
    • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
    • CAN_S

Vivado Hardware Manager

System Design - Vivado


Block Design

Block Design


PS Interfaces

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
CAN0EMIO
I2C0MIO
PJTAG0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO/GTP
PCIeMIO/GTP
SATAGTP
DisplayPortEMIO/GTP
PS Interfaces

Constrains

Basic module constrains

_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

_i_io.xdc
# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48 
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S  SC16 J3:46 B26_L1_N

set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

# Audio Codec
#LRCLK		 J3:49 
#BCLK		 J3:51 
#DAC_SDATA	 J3:53 
#ADC_SDATA	 J3:55 
set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN L14 [get_ports I2S_bclk ]
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]   

Software Design - Vitis


For Vitis project creation, follow instructions from:

Vitis


Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name


Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


Software Design -  PetaLinux


For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Activate:

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot
Changes:

  • CONFIG_I2C_EEPROM=y

  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50

  • CONFIG_SYS_I2C_EEPROM_BUS=2

  • CONFIG_SYS_EEPROM_SIZE=256

  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

  • CONFIG_SD_BOOT=y


Change platform-top.h:

 

Device Tree

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};  

/* notes:
serdes:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h
*/  

/* default */

/* sata */

&sata {
phy-names = "sata-phy";
phys = <&lane2 1  0 0 150000000>;
};

/* SD */
&sdhci0 {
	// disable-wp;
	no-1-8-v;

};

&sdhci1 {
	// disable-wp;
	no-1-8-v;

};   

/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 2 100000000>;
    maximum-speed = "super-speed";
};

/* ETH PHY */

&gem3 {
	phy-handle = <&phy0>;
	phy0: phy0@1 {
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c@2 { // PCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // TEBF0808 EEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
            eeprom: eeprom@50 {
	            compatible = "atmel,24c08";
	            reg = <0x50>;
	          };
        };
        i2c@6 { // TEBF0808 FMC  
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 PMOD P1
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
			/*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
			*/
        };
        i2c@2 { // TEBF0808 Firefly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // TEBF0808 Firefly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { //TEBF0808 CPLD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 PMOD P3
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_NVME_CORE=y
  • CONFIG_BLK_DEV_NVME=y
  • CONFIG_NVME_TARGET=y
  • CONFIG_SATA_AHCI=y
  • CONFIG_SATA_MOBILE_LPM_POLICY=0

  • CONFIG_NVM=y

  • CONFIG_NVM_PBLK=y

  • CONFIG_NVM_PBLK_DEBUG=y

  • CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software


SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338


Appx. A: Change History and Legal Notices


Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.


DateDocument Revision

Authors

Description

  • Release 2020.2
  • update document style
2020-04-06v.28John Hartfiel
  • new assembly variants
2020-03-25v.27John Hartfiel
  • script update
2020-02-25v.26John Hartfiel
  • Update requirement section
2020-01-23v.25John Hartfiel
  • Release 2019.2
2019-05-07v.24John Hartfiel
  • Release 2018.3
2018-10-26v.21John Hartfiel
  • new assembly variant

2018-08-14

v.19John Hartfiel
  • design update

2018-07-23

v.18John Hartfiel
  • new assembly variant

2018-07-20

v.16John Hartfiel
  • Release 2018.2

2018-05-17

v.14

John Hartfiel
  • new assembly variant
  • solved known issues

2018-04-30

v.13John Hartfiel
  • Update known Issues

2018-04-11

v.12John Hartfiel
  • bugfix board part files

2018-02-13

v.11John Hartfiel
  • new assembly variant
  • solved known issues
2018-01-29v.4John Hartfiel
  • Update known Issues
2018-01-18v.3John Hartfiel
  • Release 2017.4

All
Document change history.

Legal Notices

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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.







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