- Created by John Hartfiel, last modified on 24 09, 2024
Overview
Linux with basic periphery of TE0808 StarterKit (TEBF0808 Carrier).
Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
Key Features
- Vitis/Vivado 2023.2
- TEBF0808
- PetaLinux
- USB
- ETH
- MAC from EEPROM
- PCIe
- SATA
- SD
- I2C
- RGPIO
- Display Port (DP)
- user LED access
- Modified FSBL for Si5338 programming
Revision History
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2024-09-24 | 2023.2 | TE0803-StarterKit_noprebuilt-vivado_2023.2-build_4_20240923123822.zip TE0803-StarterKit-vivado_2023.2-build_4_20240923123822.zip | John Hartfiel |
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2024-08-26 | 2023.2 | TE0803-StarterKit-vivado_2023.2-build_4_20240822125103.zip TE0803-StarterKit_noprebuilt-vivado_2023.2-build_4_20240822125103.zip | John Hartfiel |
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2023-09-14 | 2022.2 | TE0803-StarterKit-vivado_2022.2-build_8_20230914124643.zip TE0803-StarterKit_noprebuilt-vivado_2022.2-build_8_20230914124643.zip | Manuela Strücker |
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2022-10-17 | 2021.2.1 | TE0803-StarterKit-vivado_2021.2-build_18_20221017093105.zip TE0803-StarterKit_noprebuilt-vivado_2021.2-build_18_20221017093105.zip | Manuela Strücker |
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2022-08-30 | 2021.2.1 | TE0803-StarterKit-vivado_2021.2-build_15_20220830131524.zip TE0803-StarterKit_noprebuilt-vivado_2021.2-build_15_20220830131524.zip | Manuela Strücker |
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2022-04-05 | 2021.2 | TE0803-StarterKit-vivado_2021.2-build_11_20220405095407.zip TE0803-StarterKit_noprebuilt-vivado_2021.2-build_11_20220405095407.zip | Manuela Strücker |
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2021-09-06 | 2020.2 | TE0803-StarterKit_noprebuilt-vivado_2020.2-build_7_20210906104631.zip TE0803-StarterKit-vivado_2020.2-build_7_20210906104617.zip | Manuela Strücker |
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2020-04-06 | 2019.2 | TE0803-StarterKit_noprebuilt-vivado_2019.2-build_9_20200406082458.zip TE0803-StarterKit-vivado_2019.2-build_9_20200406082321.zip | John Hartfiel |
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2020-03-25 | 2019.2 | TE0803-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325082516.zip TE0803-StarterKit-vivado_2019.2-build_8_20200325082450.zip | John Hartfiel |
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2020-01-23 | 2019.2 | TE0803-StarterKit_noprebuilt-vivado_2019.2-build_3_20200123065955.zip TE0803-StarterKit-vivado_2019.2-build_3_20200123065933.zip | John Hartfiel |
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2019-05-07 | 2018.3 | TE0803-StarterKit-vivado_2018.3-build_05_20190507093424.zip TE0803-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507093443.zip | John Hartfiel |
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2018-10-25 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_03_20181026141553.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_03_20181026141611.zip | John Hartfiel |
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2018-08-14 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_02_20180814103204.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip | John Hartfiel |
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2018-07-23 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip | John Hartfiel |
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2018-07-12 | 2018.2 | TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip | John Hartfiel |
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2018-05-17 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip | John Hartfiel |
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2018-04-11 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip | John Hartfiel |
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2018-02-13 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip | John Hartfiel |
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2018-02-06 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip | John Hartfiel |
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2018-02-05 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip | John Hartfiel |
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2018-01-31 | 2017.4 | TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip | John Hartfiel |
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2018-01-18 | 2017.4 | TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip | John Hartfiel |
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Release Notes and Know Issues
Issues | Description | Workaround/Solution | To be fixed version |
---|---|---|---|
Xilinx Software | Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request | use corresponding board files for the Vivado versions | -- |
MAC from EEPROM | The MAC address stored in the EEPROM is not read out and initialised correctly during start-up. | Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure. | Solved with 20220405 update |
QSPI Flash | Flash programming is not supported with boot mode QSPI or SD. | If flash programming fails, configure device for JTAG boot mode and try again or use Vivado Versions for programming. (Vivado 2020.2 or 2019.2) | -- |
Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180517 update |
USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is nessecary:
| Solved with 20180205 update |
Requirements
Software
Software | Version | Note |
---|---|---|
Vitis | 2023.2 | needed; Vivado is included into Vitis installation; Vitis classic is used at the moment for software application |
PetaLinux | 2023.2 | needed |
SI ClockBuilder Pro | --- | optional |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|
TE0803-01-02CG-1E | 2cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-02CG-1EA | 2cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-02EG-1E | 2eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-02EG-1EA | 2eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-03CG-1E | 3cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-03CG-1EA | 3cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-03EG-1E | 3eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-03EG-1EA | 3eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04CG-1EA | 4cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04CG-1EB | 4cg_2gb | REV01 | 2GB | 256MB | NA | NA | NA |
TE0803-01-04EG-1EA | 4eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04EV-1E3 | 4ev_2gb | REV01 | 2GB | 128MB | NA | 1 mm connectors | NA |
TE0803-01-05EV-1EA | 5ev_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-05EV-1IA | 5ev_i_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-02-03EG-1EB | 3eg_4gb | REV02|REV01 | 4GB | 128MB | NA | NA | NA |
TE0803-02-04EG-1E3 | 4eg_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-02-04EV-1EA | 4ev_2gb | REV02|REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-02-04EV-1E3 | 4ev_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-2AE11-A | 2cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-2BE11-A | 2eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3AE11-A | 3cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3AE11-AK | 3cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3AE10-R | 3cg_0_2gb | REV03 | 2GB | NA | NA | NA | PS MIO 3.3V, not compatible to trenz carrier |
TE0803-03-3BE11-A | 3eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3BE21-A | 3eg_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-3BE31-A | 3eg_8gb | REV03 | 8GB | 128MB | NA | NA | dual die ddr |
TE0803-03-3BI21-A | 3eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-3RI21-A | 3eg_li_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-4AE11-A | 4cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4BE11-A | 4eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4BE21-L | 4eg_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4BI21-A | 4eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-4BI21-X | 4eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0803-03-4BI61-A | 4eg_8gb | REV03 | 8GB | 128MB | NA | NA | dual die ddr |
TE0803-03-4BI61-X | 4eg_8gb | REV03 | 8GB | 128MB | NA | NA | dual die ddr |
TE0803-03-4DE11-A | 4ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4DE21-L | 4ev_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4DE21-LZ | 4ev_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4DI21-D | 4ev_i_4gb | REV03 | 4GB | 128MB | NA | NA | |
TE0803-03-4DI21-L | 4ev_i_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4GE11-A | 4eg_2_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4GE21-L | 4eg_2_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4GI11-A | 4eg_2i_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4GI21-A | 4eg_2i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-5BE11-A | 5eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-5DE11-A | 5ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-5DI21-A | 5ev_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-5DI24-A | 5ev_i_4gb | REV03 | 4GB | 512MB | NA | NA | NA |
TE0803-03-S003 | 4ev_2gb | REV03 | 2GB | 128MB | NA | NA | CAO: TE0803-03-4DE11-A |
TE0803-03-S005 | 4eg_2gb | REV03 | 2GB | 128MB | NA | NA | CAO: TE0803-03-4BI1?-A |
TE0803-04-2AE11-A | 2cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-2BE11-A | 2eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-2BE11-AK | 2eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-3AE10-R | 3cg_0_2gb | REV04 | 2GB | NA | NA | NA | PS MIO 3.3V, not compatible to trenz carrier |
TE0803-04-3AE11-A | 3cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-3AE11-AK | 3cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-3BE11-A | 3eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-3BE21-A | 3eg_4gb | REV04 | 4GB | 128MB | NA | NA | NA |
TE0803-04-3BE21-L | 3eg_4gb | REV04 | 4GB | 128MB | NA | NA | NA |
TE0803-04-4AE11-A | 4cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4AE11-AK | 4cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4AE11-AZ | 4cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4BE11-A | 4eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4BE11-AK | 4eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4BE21-L | 4eg_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4BI21-A | 4eg_i_4gb | REV04 | 4GB | 128MB | NA | NA | NA |
TE0803-04-4BI21-X | 4eg_i_4gb | REV04 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0803-04-4BI61-A | 4eg_8gb | REV04 | 8GB | 128MB | NA | NA | dual die ddr |
TE0803-04-4BI61-X | 4eg_8gb | REV04 | 8GB | 128MB | NA | NA | dual die ddr |
TE0803-04-4DE11-A | 4ev_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4DE11-AK | 4ev_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4DE11-AZ | 4ev_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-4DE21-L | 4ev_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4DE21-LZ | 4ev_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4DI21-D | 4ev_i_4gb | REV04 | 4GB | 128MB | NA | NA | |
TE0803-04-4DI21-L | 4ev_i_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4GE21-L | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4GE81-L | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-4GI21-A | 4eg_2i_4gb | REV04 | 4GB | 128MB | NA | NA | NA |
TE0803-04-5BE11-A | 5eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-5DE11-A | 5ev_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-5DI21-A | 5ev_i_4gb | REV04 | 4GB | 128MB | NA | NA | NA |
TE0803-04-S006 | 4ev_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | CAO: TE0803-04-4DE21-L |
TE0803-04-S009 | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | CAO: TE0803-04-4GE21-L |
TE0803-04-S010 | 5ev_2gb | REV04 | 2GB | 128MB | NA | NA | CAO: TE0803-04-5DE11-A |
TE0803-04-S011 | 4eg_2_4gb | REV04 | 4GB | 64MB | NA | 1 mm connectors | CAO: TE0803-04-4GE25-L |
TE0803-04-S012 | 2cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-S013 | 3cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-S014 | 4eg_2_4gb | REV04 | 4GB | 64MB | NA | 1 mm connectors | CAO: TE0803-04-4GE2?-LZ |
TE0803-04-S016 | 4cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-S017 | 2eg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-S018 | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-04-S020 | 4cg_2gb | REV04 | 2GB | 128MB | NA | NA | NA |
TE0803-04-S022 | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | CAO: TE0803-04-4GE21-LZ |
TE0803-04-S023 | 4eg_2_4gb | REV04 | 4GB | 128MB | NA | 1 mm connectors | CAO: TE0803-04-4GE81-L |
TE0803-04-S026 | 5ev_i_4gb | REV04 | 4GB | 128MB | NA | NA | CAO: TE0803-04-5DI21-A |
TE0803-04-S027 | 3cg_2gb | REV04 | 2GB | 128MB | NA | NA | CAO:TE0803-04-3AE11-A |
*used as reference
Note: Design contains also Board Part Files for TE0803 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
Carrier Model | Notes |
---|---|
TEBF0808* | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
*used as reference
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
DP Monitor | Optional HW |
USB Keyboard | Optional HW Can be used to get access to console which is show on DP |
USB Stick | Optional HW USB was tested with USB memory stick |
SATA Disk | Optional HW |
PCIe Card | Optional HW |
ETH cable | Optional HW Ethernet works with DHCP, but can be setup also manually |
SD card | with fat32 partition |
Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
Type | Location | Notes |
---|---|---|
Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts |
Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
---|---|---|
SI5338 | <project folder>\misc\PLL\Si5338_B | SI5338 Project with current PLL Configuration |
init.sh | <project folder>\misc\sd | Additional Initialization Script for Linux |
Prebuilt
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Script-File | *.scr | Distro Boot Script file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) |
Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
_create_win_setup.cmd/_create_linux_setup.sh------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide)
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
- Important: Use Board Part Files, which ends with *_tebf0808
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")TE::hw_build_design -export_prebuilt
Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
(optional) Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis (recommended)
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitisrun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Copy PetaLinux build image files to prebuilt folder
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
run on Vivado TCL (Script programs BOOT.bin on QSPI flash)TE::pr_program_flash -swapp hello_te0803
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (JTAG XMOD)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used.
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional with TEBF0808) Connect SATA Disc
- (Optional with TEBF0808) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional with TEBF0808) Connect Network Cable
Power On PCB
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
# password disabled petalinux login: root Password: root
Note: Wait until Linux boot finished
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to Zynq
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
- Control:
- LEDs: XMOD 2 (without green dot) and HD LED are accessible.
- CAN_S
System Design - Vivado
Block Design
PS Interfaces
Activated interfaces:
Type | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO(emmc) |
SD1 | MIO(sd) |
CAN0 | EMIO |
I2C0 | MIO |
PJTAG0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 | |
TTC0..3 | |
GEM3 | MIO |
USB0 | MIO/GTP |
PCIe | MIO/GTP |
SATA | GTP |
DisplayPort | EMIO/GTP |
Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
Design specific constrain
# system controller ip #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B26_L11_P #CAN TX SC18 J3:50 B26_L11_N #CAN S SC16 J3:46 B26_L1_N set_property PACKAGE_PIN G14 [get_ports BASE_sc0] set_property PACKAGE_PIN D15 [get_ports BASE_sc5] set_property PACKAGE_PIN H13 [get_ports BASE_sc6] set_property PACKAGE_PIN H14 [get_ports BASE_sc7] set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B13 [get_ports BASE_sc11] set_property PACKAGE_PIN A14 [get_ports BASE_sc12] set_property PACKAGE_PIN B14 [get_ports BASE_sc13] set_property PACKAGE_PIN F13 [get_ports BASE_sc14] set_property PACKAGE_PIN G13 [get_ports BASE_sc15] set_property PACKAGE_PIN A15 [get_ports BASE_sc16] set_property PACKAGE_PIN B15 [get_ports BASE_sc17] set_property PACKAGE_PIN J14 [get_ports BASE_sc18] set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # Audio Codec #LRCLK J3:49 #BCLK J3:51 #DAC_SDATA J3:53 #ADC_SDATA J3:55 set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ] set_property PACKAGE_PIN L14 [get_ports I2S_bclk ] set_property PACKAGE_PIN E15 [get_ports I2S_sdin ] set_property PACKAGE_PIN F15 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] # MGTs only for ZU4/5 Devices # Y6 MGT_224_CLK0_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> floating # Y5 MGT_224_CLK0_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> floating # V6 MGT_224_CLK1_P -> U5,38 -> Si5338 -> CLK1 # V5 MGT_224_CLK1_N -> U5,37 -> Si5338 -> CLK1 #set_property PACKAGE_PIN Y6 [get_ports {MGT_CLK_IN_clk_p[0]}] #set_property PACKAGE_PIN V6 [get_ports {MGT_CLK_IN_clk_p[1]}]
Software Design - Vitis
For Vitis project creation, follow instructions from:
Application
Template location: "<project folder>\sw_lib\sw_apps\"zynqmp_fsbl
TE modified 2023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
hello_te0803
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xE00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x3000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xE00000
- CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x3000000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0803_TEBF0808"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_NVMEM=y
- CONFIG_DM_RTC=y (needed for nvmem driver because of bug in uboot )
- Boot Modes:
- CONFIG_BOOT_SCRIPT_OFFSET=0x3E40000
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_OVERWRITE=y
- # CONFIG_ENV_IS_IN_FAT is not set
- # CONFIG_ENV_IS_IN_NAND is not set
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- Identification
- CONFIG_IDENT_STRING=" TE0803_TEBF0808"
Add generic boot.scr:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\u-boot\u-boot-xlnx-scr\boot.cmd.generic"
Change platform-top.h:
#no changes
Device Tree
/include/ "system-conf.dtsi" /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; //refclk1:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; refclk0:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; }; &psgtr { clocks = <&refclk0 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref0\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // bus-width bus-width = <8>; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*------------------- USB --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ ETH PHY --------------------*/ &gem3 { /delete-property/ local-mac-address; phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*----------------- SATA PHY --------------------*/ &sata { ceva,p0-burst-params = <0x13084a06>; ceva,p0-cominit-params = <0x18401828>; ceva,p0-comwake-params = <0x614080e>; ceva,p0-retry-params = <0x96a43ffc>; ceva,p1-burst-params = <0x13084a06>; ceva,p1-cominit-params = <0x18401828>; ceva,p1-comwake-params = <0x614080e>; ceva,p1-retry-params = <0x96a43ffc>; }; /*-------------------- QSPI ---------------------*/ &qspi { num-cs = <2>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 2* 16MB --> dummy for all types of this QSPI type */ spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <166000000>; //166MHz max. frequency for mt25qu512 #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR reg = <1>; }; i2c@2 { // PCIe reg = <2>; }; i2c@3 { // SFP1 TEBF0808 reg = <3>; }; i2c@4 {// SFP2 TEBF0808 reg = <4>; }; i2c@5 { // TEBF0808 EEPROM reg = <5>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; i2c@6 { // TEBF0808 FMC reg = <6>; }; i2c@7 { // TEBF0808 USB HUB reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 reg = <0>; }; i2c@1 { // i2c Audio Codec reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A reg = <2>; }; i2c@3 { // TEBF0808 Firefly B reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 reg = <4>; }; i2c@5 { //TEBF0808 CPLD reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 reg = <7>; }; }; };
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU_FREQ is not set
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_imagefeature-serial-autologin-root=y
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
SI5338
File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
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Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] |
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2024-08-26 | v.39 | John Hartfiel |
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2023-09-20 | v.38 | Manuela Strücker |
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2022-10-17 | v.36 | Manuela Strücker |
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2022-09-06 | v.35 | Manuela Strücker |
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2022-07-15 | v.33 | Manuela Strücker |
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2021-09-09 | v.29 | Manuela Strücker |
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2020-04-06 | v.28 | John Hartfiel |
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2020-03-25 | v.27 | John Hartfiel |
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2020-02-25 | v.26 | John Hartfiel |
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2020-01-23 | v.25 | John Hartfiel |
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2019-05-07 | v.24 | John Hartfiel |
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2018-10-26 | v.21 | John Hartfiel |
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2018-08-14 | v.19 | John Hartfiel |
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2018-07-23 | v.18 | John Hartfiel |
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2018-07-20 | v.16 | John Hartfiel |
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2018-05-17 | v.14 | John Hartfiel |
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2018-04-30 | v.13 | John Hartfiel |
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2018-04-11 | v.12 | John Hartfiel |
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2018-02-13 | v.11 | John Hartfiel |
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2018-01-29 | v.4 | John Hartfiel |
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2018-01-18 | v.3 | John Hartfiel |
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All | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] |
Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
Error rendering macro 'page-info'
Ambiguous method overloading for method jdk.proxy244.$Proxy3575#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
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