Page History
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| Company | Trenz Electronic GmbH |
|---|---|
| PCN Number | PCN-20230619 |
| Title | TE0726-03 to TE0726-04 Hardware Revision Change |
| Subject | Hardware Revision Change |
| Issue Date | 2023-0710-01 |
Products Affected
This change affects all Trenz Electronic TEXXXX Electronic TE0726 SoMs: TEXXXXTE0726-XX03*.
Affected Product | Replacement |
|---|
Changes
| TE0726-03-41I64-A | TE0726-04-41I94-A |
| TE0726-03-41C64-A | TE0726-04-41C94-A |
| TE0726-03-11C64-A | - |
| TE0726-03-41C74-Q | - |
| TE0726-03-41C74-R | - |
Changes
#2 Changed DDR3 SDRAM (U8) from IS43TR16256BL-125KBLI to IS43TR16256ECL-125LB2LI.
Type: Schematic Change
Reason: Provide DDR3L ECC.
Impact: DDR3L ECC available. Firmware reflects it but custom firmware needs to be updated by customer.
#1 Changed DCDC EN5311QI (U16, U17, U19, U20) to MPM3834CGPA and adapted power circuit.
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Impact: None. More microphones are usable. Minor changes in electrical characteristics.
#3 Added
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DIP switch (S1) and resistor (R152) to enable JTAG only boot mode.
Type: Schematic Change
Reason: QSPI programming problems with newer Vivado versions.
Impact: None. Fix QSPI programming problems with newer Vivado versions according to AR#00002 - QSPI Programming issues.
#4 Added on-chip DDR3 ECC option (variant dependent).
Type: Schematic Change
Reason: Enable DDR3L ECC usage.
Impact: None.
#4 Connected DDR3 ECC I2C interface to I2C bus (Camera I2C or Header I2C) via I2C level shifter (U12) and adapted corresponding circuits (C120, C122, R153
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,
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R154,
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R156, and
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R159).
Type: Schematic Change
Reason: Enable DDR3L ECC usage.
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Reason: Avoid floating signal situations for memory devices with M7 signal.
Impact: None.
#6 Added
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buffers (U24, U25) for voltage level translation for signal "DDR3-ERR_LV".
Type: Schematic Change
Reason: Enable DDR3L ECC usage.
Impact: DDR3 ECC is connected to MIO52 or MIO53 (default). Firmware reflects it but custom firmware needs to be updated by customer.
#6 Added resistor (R162) and changed resistor value for resistor (R141) to use signal "PUDC" as dual-purpuse signal.
Type: Schematic Change
Reason: Dual-use option for signal "PUDC".
Impact: None. Minor changes in electrical characteristicsFirmware reflects it but custom firmware needs to be updated by customer.
#6 Added
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diode (D7) and resistors (
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R155, R160
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) for
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voltage level translation for signal "
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DONE_LV" at CPLD (U11) to signal "DONE" at FPGA (U1).
Type: Schematic Change
Reason: Enable DDR3L ECC usage.
Improve signal voltage level. ???
Impact: None.
#7 Removed HDMI CEC functionality via not assembled resistors (R140, R42), capacitor (C127) and diode (D5) and completely removed ferrid bead (L11).
Type: Schematic Change
Reason: Improve HDMI functionality.
Impact: If HDMI CEC is used in customer firmware, firmware needs to be modified or components needs to be assembled. Please contact usImpact: DDR3 ECC is connected to MIO52 or MIO53 (default). Firmware reflects it but custom firmware needs to be updated by customer.
#7 Changed ferrid bead BKP0603HS121-T (L1...L4, L6, L7, L9, L10) to MPZ0603S121HT000.
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Impact: None. Minor changes in electrical characteristics.
#8 Connected FTDI (U3) pin ADBUS4 to signal "TCK" via resistor (R172).
Type: Schematic Change
Reason: JTAG programming improvement.
Impact: None.
#9 Changed testpoint size from 0.8 mm to 1 mm diameter for testpoints (TP2, TP4, TP6, TP8...TP14).
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