Page History

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Reason: Improve power domain handling for signal FPGA_IO.

Impact: None.

#9 Added optional diode (D3) between signal nets "PROG_B"and "INIT".

Type: Schematic Change

Reason: Optionally, keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

#5 Added diode (D3) between U21 pin 3 net nRST_in and voltage rail 3.3V.

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