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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Overview

Firmware for PCB CPLD with designator U7. CPLD Device in Chain: LCMX02-256HC

Feature Summary

Power Monitoring
Reset
LED
JTAG routing

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name	Direction	Pin	Pullup/Down	Bank Power	Description
C_

...

, Can be used to control LED D4 if no error state occurs

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Reset

PROG_B is RESIN and PG_ALL.

Power

PG_ALL is used for PROG_B Reset and LED.

PGOOD is set low, if PG_ALL failed otherwise high impedance. Internal pullup is activated.

PGOOD can be drive to low from carrier, this will be indicated by LED subsequency only.

LED

LED D4 Green
Status	Blink Sequence	Priority	Comment
Reset	********	1	external Reset is set
Power failed	*****ooo	2	PG_ALL Problem (1.8V or 3.3V)
PGOOD Low	****oooo	3	PGOOD is set low from carrier
DONE	*ooooooo	4	Module not programmed
Ready	OFF	5	Module ready and programmed

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

add PGOOD functionality
new LED status sequence

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

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REV02

REV02,REV03

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	modified-user

Revision 02 released

08 Mar 2018

v.2

REV01

REV02,REV03

John Hartfiel

Revision 01, release date 2014-07-02

2017-06-07

v.1

REV01

REV02,REV03

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Initial release

All

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Legal Notices

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	IN:Legal Notices
	IN:Legal Notices

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Green LED D4, blinking pattern according to different states
DONE	in	28	3.3V	FPGA Done signal, also connected to green LED D3. Is OFF when FPGA configured.
F_TCK / C_TCK	out	9	3.3V	FPGA JTAG
F_TDI / C_TDI	out	21	3.3V	FPGA JTAG
F_TDO / C_TDO	in	5	3.3V	FPGA JTAG
F_TMS / C_TMS	out	4	3.3V	FPGA JTAG
GND		10	3.3V	GND
GND		11	3.3V	GND
GND		12	3.3V	GND
GND		13	3.3V	GND
GND		14	3.3V	connected to GND
JTAGMODE		26	3.3V	Enable JTAG access to CPLD for Firmware update (

Trenz Electronic Documentation

Versions Compared

Old Version 4

New Version 5

Key

Table of contents

Overview

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

JTAG

Reset

Power

LED

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

Legal Notices

Table of contents

HIGH-'1' : CPLD access)
MODE	in	16	3.3V	/ currently_not_used
PG_ALL	in	27	3.3V	Power sense from 1V/1.8V/3.3V/3.3VIN
PGOOD	inout	25	3.3V	Power Good. Low, if power failed, internal pullup activated
PROG_B	out	23	3.3V	FPGA Prog_B
RESIN	in	8	3.3V	external reset from B2B
TCK / M_TCK	in	30	3.3V	B2B JTAG
TDI / M_TDI	in	32	3.3V	B2B JTAG
TDO / M_TDO	out	1	3.3V	B2B JTAG
TMS / M_TMS	in	29	3.3V	B2B JTAG
XIO	out	20	3.3V	FPGA IO from Bank14 H26