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Note

If FPGA PL is loaded over JTAG and the Zynq CPU0 has not executed FSBL successfully, then the PS PLL supplied fabric clocks do not provide any clock to the PL Fabric.

 

 

 

PL only case

 If PS supplied Fabric clocks are not required then a FPGA only design is possible without instantiating the PS7 Wrapper.

PL using PS Peripherals