Boot and configuration
The only way to configure the PL portion without using the A9 Cores is JTAG. This is possible only during lab testing and troubleshooting.
If FPGA PL is loaded over JTAG and the Zynq CPU0 has not executed FSBL successfully, then the PS PLL supplied fabric clocks do not provide any clock to the PL Fabric.
PL only case
If PS supplied Fabric clocks are not required then a FPGA only design is possible without instantiating the PS7 Wrapper.
PL using PS Peripherals
Overview
Content Tools