Page History

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Changes

#1

Type:

Reason: 

Impact:

#3 Changed DCDC EN63A0QI (U14) to MP8869SGL-Z and adapted power circuit.

Type: Schematic Change

Reason: EOL of Component.

Impact: None. Minor changes in electrical characteristics.

#3 Changed DCDCs TPS82085SIL (U5, U6, U7, U8) to MPM3834CGPA-Z and adapted power circuit.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

#3 Changed load switch TPS27081ADDCR (Q1) to MP5077GG-Z and adapted circuit.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#3 Added power supervisor STM6710LWB6F (U12, U13) and connected System controller (U3) pin 25 to net "PG_SENSE" instead of 3.3 V.

Type: Schematic Change

Reason: Improve power monitoring.

Impact: Improved power monitoring circuit by supervising additional voltage rails. If monitored voltages are out of range signal "PG_SENSE" is triggered.

#5 Added diode (D2) between signals "INIT" and "PROG_B".

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Type: BOM Change

Reason:EOL of component.

Impact: None.

#20 Signal trace lengths changed

Type: PCB change

Reason: Result of changes above.

Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0713 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

#5 Added common mode voltage setting resistors (R62, R64, R65, R66) for clock signals "PLL_CLK_P" and "PLL_CLK_N" termination.

Type: Schematic Change

Reason: Improve clock termination.

Impact: None.

#5 Connected signal "RD_N" to FPGA via level translator (U10).

Type: Schematic Change

Reason: Enable 245 Synchronous FIFO Mode.

Impact: None.

#5 Added capacitor (C174) for signal "FTDI_RESET_N".

Type: Schematic Change

Reason: Follow FTDI specification.

Impact: None.

#5 Added pull-up resistor (R76) option and pull-down resistor (R78) option for signal "GPIO_0".

Type: Schematic Change

Reason: Increase setting flexibility for FT600Q.

Impact: None.

#5 Added pull-up resistor (R77) option and pull-down resistor (R79) option for signal "GPIO_1".

Type: Schematic Change

Reason: Increase setting flexibility for FT600Q.

Impact: None.

#5 Added pull-up resistor (R74) (default: fitted) and pull-down resistor (R75) (default: not fitted) for PUDC_B handling for signal "DATA4".

Type: Schematic Change

Reason: Follow AMD recommendation.

Impact: None.

#5 Added pull-up resistor (R63) for signal "OE_N".

Type: Schematic Change

Reason: Disable 245 Synchronous FIFO Mode.

Impact: None.

#5 Added pull-up resistor (R72) for signal "PROG_B".

Type: Schematic Change

Reason: Setup PROGRAM_B_0 functionality externally.

Impact: None.

#5 Added series termination resistor (R70) connecting signals "F_CK" and "FIFO_CLK".

Type: Schematic Change

Reason: Signal termination.

Impact: None.

#5 Added series termination resistor (R73) connecting signals "SPI_SCK" and "SPI_SK".

Type: Schematic Change

Reason: Signal termination.

Impact: None.

#5 Removed testpoints from bottom PCB side for signals "3.3VIN", "RESIN", "JTAGEN", "TMS", "TCK", "TDI", and "TDO".

Type: Schematic Change

Reason: Optimize placement.

Impact: None.

#5 Added testpoints (TP4, TP23, TP24, TP25, ??? TP26).

Type: Schematic Change

Reason: Optimize placement.

Impact: None.

#20 Added legal notices, system and power overview. Updated revision history. Updated page count and order. 

Type: Documentation Update

Reason: Documentation improvement.

Impact: None.

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