Page History
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Zynq-7000 All Programmable SoC
System Controller CPLD
Programmable clock generator
10/100/1000 Mbps Ethernet PHY
- DDR3-SDRAM
Hi-Speed USB 2.0 ULPI Transceiver
B2B-Connector
JM1
JM2
JM3
Key Features
Industrial-grade Xilinx Zynq-7000 (Z-7015, Z-7030) SoM
- Rugged for shock and high vibration
- 2 × ARM Cortex-A9
- 10/100/1000 tri-speed gigabit Ethernet transceiver PHY
- MAC Address EEPROM
- 32-Bit wide 1 GByte DDR3 SDRAM
- 32 MByte QSPI Flash memory
- Programmable Clock Generator
- Transceiver Clock (default 125 MHz)
- Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on board-to-board connectors
- 4 GTP/GTX (high-performance transceiver) lanes
- GTP/GTX (high-performance transceiver) clock input
- USB 2.0 high-speed ULPI transceiver
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
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IC | Designator | PS7 | MIO | Notes | |
---|---|---|---|---|---|
SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | |
EEPROM I2C | 24AA025E48 | U19 | I2C1 | MIO48, MIO49 | EEPROM for MAC Address |
RTC | ISL2020 | U16 | I2C1 | MIO48, MIO49 | Temperature compensated real time clock |
RTC Interrupt | ISL2020 | U16 | GPIO | MIO47 | Real Time Clock Interrupt |
Clock PLL | Si5338 | U10 | I2C1 | MIO48, MIO49 | Low jitter phase locked loop |
LED | D4 | GPIO | MIO7 | ||
USB | USB3320 | U6 | USB0 | MIO28..MIO39 | |
USB Reset | GPIO | MIO51 | |||
Ethernet | 88E1512 | U7 | ETH0 | MIO16..MIO27 | |
Ethernet Reset | GPIO | MIO50 |
Default MIO mapping:
MIO | Configured as | B2B | Notes |
---|---|---|---|
0 | GPIO | JM1-87 | B2B |
1 | QSPI0 | - | SPI Flash-CS |
2 | QSPI0 | - | SPI Flash-DQ0 |
3 | QSPI0 | - | SPI Flash-DQ1 |
4 | QSPI0 | - | SPI Flash-DQ2 |
5 | QSPI0 | - | SPI Flash-DQ3 |
6 | QSPI0 | - | SPI Flash-SCK |
7 | GPIO | - | Green LED D4 |
8 | QSPI0 | - | SPI Flash-SCKFB |
9 | JM1-91 | B2B | |
10 | JM1-95 | B2B | |
11 | JM1-93 | B2B | |
12 | JM1-99 | B2B | |
13 | JM1-97 | B2B | |
14 | UART0 | JM1-92 | B2B |
15 | UART0 | JM1-85 | B2B |
16..27 | ETH0 | RGMII | |
28..39 | USB0 | ULPI | |
40 | SDIO0 | JM1-27 | B2B |
41 | SDIO0 | JM1-25 | B2B |
42 | SDIO0 | JM1-23 | B2B |
43 | SDIO0 | JM1-21 | B2B |
44 | SDIO0 | JM1-19 | B2B |
45 | SDIO0 | JM1-17 | B2B |
46 | GPIO | - | Ethernet PHY LED2/INTn Signal |
47 | GPIO | - | RTC Interrupt |
48 | I2C1 | - | SCL on-board I2C |
49 | I2C1 | - | SDA on-board I2C |
50 | GPIO | - | ETH0 Reset |
51 | GPIO | - | USB Reset |
52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
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JTAG access to the Xilinx Zynq-7000 device is provided through connector JM2.
Signal | B2B Pin |
---|---|
TCK | JM2: 99 |
TDI | JM2: 95 |
TDO | JM2: 97 |
TMS | JM2: 93 |
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LED | Color | Connected to | Notes |
---|---|---|---|
D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
D3 | red | SC | Global status LED. |
D4 | green | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
Note |
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LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured. |
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This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
LED D3 is used by the SC as global status LED.
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Ethernet
The TE0715 is populated with a Marvell Alaska 88E1512 Gigabit Ethernet PHY. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signallingsignaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3.
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Note: LED1 is connected to PL via level-shifter implemented in system controller CPLD.
USB
The USB PHY USB3320 from Microchip is used on the TE0715. The ULPI interface is conected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
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This RTC IC is supported in Linux so it can be used as hwclock device.
PLL
A silicon labs Silicon Labs I2C-programmable clock generator Si5338A (U10) is populated on the module. The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.
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Input/Output | Default Frequency | Notes |
---|---|---|
IN1/IN2 | Externally supplied | need decoupling on base board |
IN3 | 25MHz | Fixed input clock |
IN4 | - | not available and not used |
IN5/IN6 | 125MHz | Ethernet PHY output clock |
CLK0 | - | not used, disabled |
CLK1 | - | not used, disabled |
CLK2 A/B | 125MHz | MGT reference clock 1 |
CLK3A | 125MHz | Bank 34 clock input |
CLK3B | - | not used, disabled |
MAC-Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used on the TE0715. It has a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM). The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
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Warning |
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TE0715-xx-30 has several HP banks on B2B Connectors, those banks have maximal Voltage tolerance of 1.8V please check special instructions for the Baseboard use with TE0715-xx-30 |
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For startup, a power supply with minimum current capability of 3A is recommended.
Note |
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VIN and 3.3VIN can be connected to the same source (3.3 V). |
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Bank | Voltage | TE0715-xx-15 | TE0715-xx-30 |
---|---|---|---|
500 MIO0 | 3.3V | ||
501 MIO1 | 1.8V | ||
502 DDR | 1.5V | ||
0 Config | 3.3V | ||
13 HR | User | Max 3.3V | Max 3.3V |
34 HR/HP | User | Max 3.3V | Max 1.8V |
35 HR/HP | User | Max 3.3V | Max 1.8V |
System Controller I/O Pins
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Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS Subsystem main clock |
ETH PHY reference | 25 MHz | U9 | - | |
USB PHY reference | 52 MHz | U15 | - | |
PLL reference | 25 MHz | U18 | - | |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from base |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz |
Initial Delivery state
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | Empty, not programmed | Valid MAC Address from manufacturer |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
Hardware Revision History
Revision | Changes |
---|---|
01 | Current Hardware Revision, no changes |
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Parameter | Min on 7015 device | Max on 7015 device | Min on 7030 device | Max on 7030 device | Units | Notes |
---|---|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | -0.4 | 3.6 | V | |
PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | -0.5 | 3.6 | V | |
PL IO Bank supply voltage for HP I/O banks (VCCO) | - | - | -0.5 | 2.0 | V | |
I/O input voltage for HR I/O banks | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V | |
I/O input voltage for HP I/O banks | - | - | -0.55 | VCCO+0.55 | V | |
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards | -0.4 | 2.625 | -0.4 | 2.625 | V | |
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.26 | -0.5 | 1.26 | V | |
Voltage on JTAG pins | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V | All dedicated pins (JTAG and configuration) are powered by VCCO_0 (refer to Xilinx UG865) |
Storage Temperature | -40 | +100 | -40 | +100 | C |
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Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in mm.
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Temperature Ranges
Commercial grade modules
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26 g | Plain module |
8.8 g | Set of bolts and nuts |
Disclaimer
Include Page | ||||
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Document Change History
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date | revision | authors | description |
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2016-03-31 | Thorsten Trenz, Antti Lukats, Philipp Bernhardt | initial version |