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The Trenz Electronic TE0715 is a System on Module (SoM) based on AMD Zynq-7000 SoC with a Quad GTP transceiver, DDR3 SDRAM, Flash memory, Gigabit Ethernet PHY, a USB 2.0 PHY and powerful switching-mode power supplies for all on-board voltages. A large number of configurable IOs is provided via rugged high-speed stacking strips. All Trenz Electronic SoMs in the 4 x 5 cm form factor are mechanically compatible.
Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.
SoC/FPGA
RAM/Storage
DDR3 SDRAM 1 GByte 3)
On Board
System Controller (SC)
Interface
Power
Dimension
50 mm × 40 mm
Notes
1) Available as assembly variant or upon request.
2) Sockets CLG484 and SBG484 are footprint-compatible.
3) Other sizes/devices, which are pin/package-compatible, upon request.
4) IO type allocation differs with SoC variant.
Storage device name | Content | Notes |
|---|---|---|
System Controller, U26 | Firmware | Visit TE0715 CPLD Firmware / TE0715 CPLD for more information. |
QSPI Flash, U14 | Not programmed | |
Programmable Clock Generator, U10 | Configuration | |
| EEPROM, U19 | Not programmed | Contains write protected Unique Node ID / MAC. |
The programmable Clock Generator (Si5338A) is used to generate four different clocks from oscillator U18 (25 MHz) connected to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B connector JM3 (CLKIN2) or by IN5 from Ethernet PHY U7 (125 MHz).
The Si5338 output frequency to the FPGA clocks can be programmed . An I2C bus is physically connecting the FPGA (master) and clock generator (slave). The I2C logic needs to be created in the FPGA to use this capability. See the reference design section for more information.
CLK Output I Net Name I Device.Pin | Default Frequency [MHz] | IO Standard | Notes |
|---|---|---|---|
| CLK0A/B | - | - | Not used/connected. |
| CLK1A/B | - | - | Not used/connected. |
| CLK2A/B | CLK2_P/N / MGT_CLK1_P/N | U5G.U5/V5 | 125 | LVDS18 | GTP transceiver clock. |
| CLK3A | FCLK125 | U5B.K2 | 50 | CMOS18 | DDR interface |
| CLK3B | - | - | Not used/connected. |
The on-board I2C devices are connected to the Zynq SoC bus master at IO bank 501. As bank 501 is fixed to 1.8V, this requires a voltage-level translator for the 3.3V I2C slave devices. Table below lists I2C slave device addresses and functions:
Device | Designator | I2C Address | Notes |
|---|---|---|---|
24AA025E48 Serial EEPROMs with EUI-48™ node identity. | U19 | 0x50 | |
ISL12020M Low-power RTC with battery backed SRAM. | U16 | 0x6F | |
ISL12020M Battery backed SRAM integrated into RTC. | U16 | 0x57 | |
SI5338A Programmable quad clock generator. | U10 | 0x70 |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
| B2B | JM1 | IO | 48 SE / 24 DIFF | |
| B2B | JM1 | IO | 8 SE / 4 DIFF | |
| B2B | JM1 | IO | 6 SE / 4 DIFF | |
| B2B | JM1 | ETH MDI | 8 | |
| B2B | JM2 | IO | 48 SE / 24 DIFF | |
| B2B | JM2 | IO | 18 SE / 9 DIFF | |
| B2B | JM2 | IO | 2 SE | |
| B2B | JM2 | JTAG | 4 | |
| B2B | JM3 | IO | 16 SE / 8 DIFF | |
| B2B | JM3 | MGT GTP | 4 | |
| B2B | JM3 | Clock in MGT GTP | 2 | |
| B2B | JM3 | Clock in | 2 | |
| B2B | JM3 | USB OTG | 3 | |
| B2B | JM3 | ETH SGMII | 4 |
Test Point | Signal | Notes |
|---|---|---|
TP1 | VIN | |
TP2 | DDR_PWR | |
TP3 | 1.8V | |
TP4 | 3.3V | |
TP5 | VTT | |
TP6 | VTTREF | |
TP7 | 3.3VIN | |
TP8 | 1.2V_MGT | |
TP9 | 1V | |
TP10 | GND | |
TP11 | GND | |
TP12 | GND | |
TP14 | PG_ALL | |
TP15 | PS-CLK | |
| TP18 | VCCIO34 | |
| TP19 | VCCIO35 | |
| TP20 | PS-POR-B |
Chip/Interface | Designator | Connected To | Notes |
|---|---|---|---|
SoC | U5 |
| |
DDR3 RAM | U12/U13 |
| |
QSPI Flash | U14 |
| |
System Controller | U26 |
| Visit TE0715 CPLD Firmware / TE0715 CPLD for further information / firmware description. |
Ethernet PHY | U7 |
| |
USB 2.0 PHY | U6 |
| |
Voltage level translator | U20 |
| |
Clock Generator | U10 |
| Visit chapter Initial Delivery State / Programmable Clock Generator for further information. |
RTC | U16 |
| |
EEPROM | U19 |
| Contains unique Node Identity / MAC. |
Oscillator | U9 |
| 25 MHz |
| Oscillator | U11 |
| 33.3 MHz |
| Oscillator | U15 |
| 52 MHz |
| Oscillator | U18 |
| 25 MHz |
Signal Name | Connector.Pin | Direction1) | Description |
|---|---|---|---|
| EN1 | JM1.28 | Signal dependent | SoM power enable or SC JTAG TDI. 2) |
| PGOOD | JM1.30 | Signal dependent | Power good signal, additional boot mode pin or SC JTAG TDO. 2) Active high when all on-module power supplies are working properly. |
| MODE | JM1.32 | Signal dependent | Sets the SoM boot source/mode or functions as SC JTAG TCL. 2) |
| NOSEQ | JM1.7 | Signal dependent | Can be used as IO signal, accessible via SoC I2C or as SC JTAG TMS. 2) |
| JTAGEN | JM1.89 | IN | Enables SC JTAG port, when high. |
| RESIN | JM2.18 | IN | Reset signal to the SoM. |
VBUS_V_EN USB_VBUS | JM3.53 JM3.55 | OUT IN | USB OTG VBus enable. Voltage state signal to SoM. |
| TDI | JM2.95 | IN | SoC JTAG TDI. |
| TDO | JM2.97 | OUT | SoC JTAG TDO. |
| TCK | JM2.99 | IN | SoC JTAG TCK. |
| TMS | JM2.93 | IN | SoC JTAG TMS. |
MIO14 MIO15 | JM1.92 JM1.87 | Signal dependent | SoC UART. |
| VCCIO13 | JM1.9 / JM1.11 | IN | SoC IO Bank supply from carrier |
| VCCIO34 | JM2.5 | IN | SoC IO Bank supply from carrier |
| VCCIO35 | JM2.7/JM2.9 | IN | SoC IO Bank supply from carrier |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) When JTAGEN is high, the signal works as part of a JTAG connection to program or update the System Controller.
Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
|---|---|---|---|
| 3.3VIN | JM1.13 / JM1.15 | IN | |
| VIN | JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8 | IN | |
| VBAT_IN | JM1.79 | IN | |
| VCCIO13 | JM1.9 / JM1.11 | IN | |
| VCCIO34 | JM2.5 | IN | |
| VCCIO35 | JM2.7 / JM2.9 | IN | |
| 3.3V / VREF_JTAG | JM2.91 | OUT | |
| 1.8V | JM1.39 | OUT | |
| DDR_PWR | JM2.19 | OUT |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration SoM / Carrier signal setup. | |
| 1 | 3.3VIN | 3.3 V (± 5 %) | - | Main Power supply. Supplies System Controller directly. | |
| 2 | VIN | 3.3 V (± 5 %) | - | Main Power supply. | |
| 3 | EN1 | 3.3 V (± 5 %) | - | Enable SoM. | |
| 4 | PGOOD | 3.3 V (± 5 %) | - | SoM power good signal. | All SoM power sources are available. |
| 6 | VCCIO13 | - | - | Enable FPGA bank IO supply voltages. |
Refer to Trenz 4 x 5 SoM Integration Guide, FAQ - PCBDesign, AMD data sheet DS187 (for XC7Z012S / XC7Z015) or DS191 (for XC7Z030) for more information.
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
| Order number | Connector on baseboard | compatible to | Mating height |
|---|---|---|---|
| 23836 | REF-189016-01 | LSHM-150-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-150-03.0-L-DV-A-S-K-TR | LSHM-150-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 23838 | REF-189016-02 | LSHM-150-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-150-06.0-L-DV-A-S-K-TR | LSHM-150-06.0-L-DV-A-S-K-TR | 10.0mm | |
| 26125 | REF-189017-01 | LSHM-130-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-130-03.0-L-DV-A-S-K-TR | LSHM-130-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 24903 | REF-189017-02 | LSHM-130-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-130-06.0-L-DV-A-S-K-TR | LSHM-130-06.0-L-DV-A-S-K-TR | 10.0mm |
The module can be manufactured using other connectors upon request.
The LSHM connector speed rating depends on the stacking height; please see the following table:
| Stacking height | Speed rating |
|---|---|
| 12 mm, Single-Ended | 7.5 GHz / 15 Gbps |
| 12 mm, Differential | 6.5 GHz / 13 Gbps |
| 5 mm, Single-Ended | 11.5 GHz / 23 Gbps |
| 5 mm, Differential | 7.0 GHz / 14 Gbps |
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
| File | Modified | |
|---|---|---|
| PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File lshm_dv.pdf LSHM catalog page | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File tc0929--2611_qua(1).pdf Shock and vibration report | Apr 07, 2016 by Thorsten Trenz | |
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This TRM is generic for all variants.
Module variants are described here: Article Number Information. Please contact us for options.
Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
| 3.3VIN | Supply power from carrier. Powers SC directly. | –0.5 | 3.6 | V |
| VIN | Supply power from carrier. | -0.3 | 6 | V |
| VBAT_IN | SoC, RTC/Volatile Memory supply. | -0.3 | 6 | V |
| VCCIO13 | IO Bank supply for SoM. | –0.5 | 3.6 | V |
| VCCIO34 | IO Bank supply for SoM. | –0.5 –0.5 | 3.6 1) 2.0 2) | V V |
| VCCIO35 | IO Bank supply for SoM. | –0.5 –0.5 | 3.6 1) 2.0 2) | V V |
1) The SoC's XC7Z012S / XC7Z015 feature only HR Banks, which are limited to a maximum of 3.6 V.
2) The SoC's XC7Z030 IO Banks 34 and 35 are HP Banks, which are limited to a maximum of 2 V.
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.
These categories do not take into account the entire custom system consisting of:
Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
Cooling solution, active and or passive cooling.
Climate or environmental conditions besides ambient temperature range.
Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.
Classification of the module can be locked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| 3.3VIN | 3.15 | 3.45 | V | |
| VIN | 3.135 | 5.25 | V | |
| VBAT_IN | 2.91 | 3.09 | V | |
| VCCIO13 | 1.164 | 3.399 | V | |
| VCCIO34 | 1.164 1.164 | 3.399 1) 1.854 2) | V V | |
| VCCIO35 | 1.164 1.164 | 3.399 1) 1.854 2) | V V |
1) The SoC's XC7Z012S / XC7Z015 feature only HR IO Banks, which are limited to a maximum of 3.3 V.
2) The SoC XC7Z030 IO Banks 34 and 35 are HP IO Banks, which are limited to a maximum of 1.8 V.
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
All dimensions are shown in millimeters.
Trenz shop TE0715 overview page* | |
|---|---|
*) Module article name encoding table: 7 Series Zynq-7000 based modules
The hardware revision number is located on the PCB next to the module identifier, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
| 2022-03 | 05 | 1. SI5338 OTP content update 2. Revised power supply circuit: replaced obsolete parts U1, U2, U3,U8,U24, Q1. 12. Replace EN6347QI (U1) by MPM3840GQV-Z. | |
| 2016-07 | 04 | 1. Change DDR3 RAM (U12, U13) from IM4G16D3FABG-125I to IS43TR16256BL-125KBLI. 4. Replaced Level translator LFXLA101L6X (U21) by FXLH1T45L6X. 5. Fixed Xilinx AR# 65240. | |
| 2015-07 | 03 | ||
| 2015-04 | 02 | ||
| 2015-02 | 01 |
Date | Revision | Contributors | Description |
|---|---|---|---|
| |||
2026-02-19 | v.96 | Kilian Jahn |
|
2024-06-19 | v.90 | Waldemar Hanemann |
|
| 2021-06-21 | v.87 | John Hartfiel |
|
| 2018-07-06 | v.86 | John Hartfiel |
|
2017-11-14 | v.85 | John Hartfiel |
|
| 2017-09-10 | v.82 | Jan Kumann |
|
| 2017-06-07 | v.64 | Jan Kumann |
|
| 2017-03-02 | v.59 | Thorsten Trenz |
|
| 2017-02-10 | v.58 | Thorsten Trenz |
|
| 2017-01-25 | v.55 | Jan Kumann |
|
| 2017-01-14 | v.50 | Jan Kumann |
|
| 2016-11-15 | v.45 | Thorsten Trenz |
|
| 2016-10-18 | v.40 | Ali Naseri |
|
| 2016-06-28 | v.38 | Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann |
|
| 2016-04-27 | v.33 | Thorsten Trenz, Emmanuel Vassilakis |
|
| 2016-03-31 | v.10 | Philipp Bernhardt, Antti Lukats |
|
Table 22: Document change history.
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
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