Page History
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Note |
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JTAGEN pin in JM1 should be kept low or grounded for normal operation. |
Clocking
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 Mhz | U11 | PS_CLK | PS Subsystem main clock |
ETH PHY reference | 25 MHz | U9 | - | |
USB PHY reference | 52 MHz | U15 | - | |
PLL reference | 25 MHz | U18 | - | |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from base |
GT REFCLK1 | 125 Mhz | U10 Si5338 | U5/V5 | Default clock is 125 MHz |
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Overview
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