Page History
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Parameter | Min on 7015 device | Max on 7015 device | Min on 7030 device | Max on 7030 device | Units | Notes | |||||
---|---|---|---|---|---|---|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | -0.3 | 6.0 | V | ||||||
Vin33 supply voltage | -0.4 | 3.6 | -0.4 | 3.6 | V | ||||||
PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | -0.5 | 3.6 | V | ||||||
PL IO Bank supply voltage for HP I/O banks (VCCO) | - | - | -0.5 | 2.0 | V | ||||||
I/O input voltage for HR I/O banks | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V | ||||||
I/O input voltage for HP I/O banks | - | - | -0.55 | VCCO+0.55 | V | ||||||
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards | -0.4 | 2.625 | -0.4 | 2.625 | V | ||||||
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.26 | -0.5 | 1.26 | V | ||||||
Voltage on Module JTAG pins | -0.4 | VCCO+0.55 | -0.4 | VCCO+0.55 | V |
|
| V | All dedicated pins (JTAG and configuration) are powered by VCCO_0 (refer to Xilinx UG865) | ||
Storage Temperature | -40 | +100 | -40 | +100 | C |
Note |
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Please check Xilinx Datasheet for complete list of Absolute maximum ratings for the Zynq device. |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
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