Page History
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Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | -0.3 | 7 | V | TPS82085SIL / EN63A0QI data sheet |
| DCDCIN | -0.3 | 7 | V | TPS82085SIL / TPS51206 data sheet |
| LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
| GT_DCDC | -0.3 | 7 | V | TPS82085SIL data sheet |
| PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
| PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
| VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
| VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
| MGT clock absolute input voltage | -0.5 | 1.3 | V | Xilinx document DS925 |
MGT Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
| "Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
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| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | 3.3 | 6 | V | EN63A0QI / TPS82085SIL data sheet |
| DCDCIN | 3.3 | 6 | V | TPS82085SIL / TPS51206PSQ data sheet |
| LP_DCDC | 3.3 | 3.6 | V | TPS82085SIL / TPS3106 data sheet |
| GT_DCDC | 3.3 | 6 | V | TPS82085SIL data sheet |
| PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
| PLL_3V3 | 3.3 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
| VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| PL bank reference voltage VREF pin | -0.5 | 2 | V | Xilinx DS925 data sheet |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
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