Page History

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1. Xilinx ZYNQ UltraScale+ XCZU9EG ZU7EV-1FBVB900 MPSoC, U1
2. EN63A0QI 12A PowerSoC DC-DC converter, U4
3. TI TPS72018 LDO @1.8V, U6
4. TI TPS74401 LDO @0.9V, U14
5. TI TPS74401 LDO @1.2V, U28
6. TI TPS72018 LDO @1.8V, U6
7. Quarz Crystal @50.000MHz, Y1
8. Low-power programmable oscillator @ 3325.333333 000000 MHz (PS_CLKIN0 for U5), U32
9. Red LED (DONE), D1
10. U25
11. TI TPS74801 LDO @1.8V, U10
12. TI TPS74801 LDO @0.9V, U8
13. 8 Gbit (512Mx16) 256Mx16 DDR4-2400 SDRAM, U12
14. 256Mx16 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
15. 256Mx16 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
16. 256Mx16 8 Gbit (512Mx16) DDR4-2400 SDRAM, U312A PowerSoC DC-DC converter, U4
17. Quartz crystal, Y1
18. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
19. 10-channel programmable PLL clock generator, U5
20. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4J3
21. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2J1
22. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3J4
23. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
24. Quartz crystal, Y2
25. 256 Mbit serial NOR Flash memory, U7
26. J2
27. 1.8V, 512 Mbit QSPI flash memory ,U17
28. 1.8V, 512 Mbit QSPI flash memory, U7
29. TI TPS72018 LDO @1.8V, U27256 Mbit serial NOR Flash memory, U17

Initial Delivery State

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Table 4: MGT lanes

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

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Table 5: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

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Table 4: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

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4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.

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ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

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Table 4: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board, and clock inputs are also provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Table 5: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

Table 4: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 6: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

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Table 6: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

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Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

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JM1-19

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JM1-21

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63

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Table 8: TE0807-01 PS MIO mapping

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Revision History

Hardware Revision History

Table 20: Hardware revision history table

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