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The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.
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The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2 J2 depends on its configured firmware. CPLD can be set into JTAG chain via S2-1 DIP Switch. Refer to the Resources Site of the TE0790 the TE0790 CPLD Firmware for more information about the currently available System Controller CPLD firmware and for download.
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Table 8: DIP-switch S2 power setting description. *Attention: don't supply voltage from base if pin sourced from USB! For more details see Power supply of the adapter board section.
User Push Button
The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.
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Power supply of the adapter board
The adapter on-board's peripherals are powered XMOD can be powered via USB or with 3.3V as supply voltage. If 3.3V and VIO is supplied only by the on-board LDO converter U3 (switches S2-3 and S2-4 ON), the XMOD adapter board has max. output current of ~100mA.
If module is powered from base then S2-4 (and most likely S2-3 (VIO) too) must be OFFon J2 pins, depending on DIP-switch settings. Max. ~100mA for external components are available on J2 3.3V Pin, if the power supply via USB is used.
Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 determines the configuration of the on-board voltages:
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Date | Revision | Contributors | Description | ||||||||
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| Ali Naseri |
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2017-10-26 | v.27 | John Hartfiel |
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| 2017-10-19 | v.26 | Ali Naseri |
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Table 15: Document change history.
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