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changes.mady.by.user Antti Lukats

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titleFigure 1: TE0807-02 03 block diagram


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Main Components

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titleFigure 2: TE0807-02 03 main components


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Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

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PS MIOFunctionConnected to
0SPI0U7-B2, CLK
1SPI0U7-D2, DO/IO1
2SPI0U7-C4, WP/IO2
3SPI0U7-D4, HOLD/IO3
4SPI0U7-D3, DI/IO0 
5SPI0 U7-C2, CS
6N/ANot connected
7SPI1U17-C2, CS
8SPI1U17-D3, DI/IO0
9SPI1U17-D2, DO/IO1
10SPI1U17-C4, WP/IO2
11SPI1U17-D4, HOLD/IO3
12SPI1U17-B2, CLK
13 ... 77user dependentB2B connector J2

Table 11: TE0807-02 03 PS MIO mapping

On-board Peripherals

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Table 12: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-02 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.

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titleFigure 3: TE0807-02 03 Power Distribution Diagram


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titleFigure 4: TE0807-02 03 Power-on Sequence Diagram


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Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins

Directions

Note
PL_DCIN151, 153, 157, 159---Input-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

--Input-
LP_DCDC-138, 140, 142, 144--Input-
PS_BATT-125--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-135--Output

Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-

Table 19: TE0807-02 03 power rails

Bank Voltages

BankTypeSchematic NameVoltageReference Input VoltageVoltage Range
47HDVCCO47user-1.2V to 3.3V
48HDVCCO48user-1.2V to 3.3V
64HPVCCO64userVREF_64, pin J4-881.2V to 1.8V
65HPVCCO65userVREF_65, pin J4-151.2V to 1.8V
66HPVCCO66userVREF_66, pin J1-1081.2V to 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 20: TE0807-02 03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

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DateRevision

Notes

PCN LinkDocumentation Link
2020-06-0503current available module revisionPCN-20200511TE0807-03
-02current available module revision-TE0807-02
-01first production release-TE0807-01

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Date

Revision

Contributors

Description

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  • Updated to REV03

v.24

Antti Lukats

  • Corrected B2B include macro

v.22John Hartfiel
  • typo correction SI5345 I2C address
  • typo B2B Pin of CLK signals

v.20Ali Naseri
  • initial document

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