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Table 3: Selectable boot modes by dedicated boot mode pins.
For functional details see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).
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Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 02 SoM.
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
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Bank | Type | Lane | Signal Name | B2B Pin | FPGA Pin |
---|---|---|---|---|---|
224 | GTH | 0 |
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1 |
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2 |
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3 |
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225 | GTH | 0 |
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1 |
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2 |
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3 |
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226 | GTH | 0 |
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1 |
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2 |
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3 |
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227 | GTH | 0 |
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1 |
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2 |
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3 |
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505 | GTR | 0 |
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1 |
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2 |
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3 |
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Table 45: MGT lanes
There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board, and clock inputs are also . The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
B224_CLK0_P | 224 | B2B, J3-62 | MGTREFCLK0P_224, R8 | Supplied by the carrier board |
B224_CLK0_N | 224 | B2B, J3-60 | MGTREFCLK0N_224, R7 | Supplied by the carrier board |
B224_CLK1_P | 224 | U5, CLK4_P | MGTREFCLK1P_224, N8 | On-board Si5345A |
B224_CLK1_N | 224 | U5, CLK4_N | MGTREFCLK1N_224, N7 | On-board Si5345A |
B225_CLK0_P | 225 | B2B, J3-67 | MGTREFCLK0P_225, L8 | Supplied by the carrier board |
B225_CLK0_N | 225 | B2B, J2-65 | MGTREFCLK0N_225, L7 | Supplied by the carrier board |
B225_CLK1_P | 225 | U5, CLK3_P | MGTREFCLK1P_225, J8 | On-board Si5345A |
B225_CLK1_N | 225 | U5, CLK3_N | MGTREFCLK1N_225, J7 | On-board Si5345A |
B226_CLK0_P | 226 | U5, CLK2_P | MGTREFCLK0P_226, H10 | On-board Si5345A |
B226_CLK0_N | 226 | U5, CLK2_N | MGTREFCLK0N_226, H9 | On-board Si5345A |
B226_CLK1_P | 226 | B2B, J3-61 | MGTREFCLK1P_226, F10 | Supplied by the carrier board |
B226_CLK1_N | 226 | B2B, J3-59 | MGTREFCLK1N_226, F9 | Supplied by the carrier board |
B227_CLK0_P | 227 | U5, CLK1_P | MGTREFCLK0P_227, D10 | On-board Si5345A |
B227_CLK0_N | 227 | U5, CLK1_N | MGTREFCLK0N_227, D9 | On-board Si5345A |
B227_CLK1_P | 227 | B2B, J2-22 | MGTREFCLK1P_227, B10 | Supplied by the carrier board |
B227_CLK1_N | 227 | B2B, J2-24 | MGTREFCLK1N_227, B9 | Supplied by the carrier board |
B505_CLK0_P | 505 | B2B, J2-10 | PS_MGTREFCLK0P_505, M23 | Supplied by the carrier board |
B505_CLK0_N | 505 | B2B, J2-12 | PS_MGTREFCLK0N_505, M24 | Supplied by the carrier board |
B505_CLK1_P | 505 | B2B, J2-16 | PS_MGTREFCLK1P_505, L25 | Supplied by the carrier board |
B505_CLK1_N | 505 | B2B, J2-18 | PS_MGTREFCLK1N_505, L26 | Supplied by the carrier board |
B505_CLK2_P | 505 | U5, CLK5_P | PS_MGTREFCLK2P_505, K23 | On-board Si5345A |
B505_CLK2_N | 505 | U5, CLK5_N | PS_MGTREFCLK2N_505, K24 | On-board Si5345A |
B505_CLK3_P | 505 | U5, CLK6_P | PS_MGTREFCLK3P_505, H23 | On-board Si5345A |
B505_CLK3_N | 505 | U5, CLK6_N | PS_MGTREFCLK3N_505, H24 | On-board Si5345A |
Table 56: MGT reference clock sources
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JTAG Signal | B2B Connector Pin |
---|---|
TCK | J2-120 |
TDI | J2-122 |
TDO | J2-124 |
TMS | J2-126 |
Table 47: B2B connector pin-out of JTAG interface.
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Signal | B2B Connector Pin | Function |
---|---|---|
DONE | J2-116 | PL configuration completed. |
PROG_B | J2-100 | PL configuration reset signal. |
INIT_B | J2-98 | PS is initialized after a power-on reset. |
SRST_B | J2-96 | System reset. |
MODE0 ... MODE3 | J2-109/J2-107/J2-105/J2-103 | 4-bit boot mode pins. For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'. |
ERR_STATUS / ERR_OUT | J2-86 / J2-88 | ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU). ERR_STATUS indicates a secure lock-down state. |
PUDC_B | J2-127 | Pull-up during configuration (pulled-up to PL_1V8). |
Table 58: B2B connector pin-out of MPSoC's PS configuration bank.
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Signal | B2B Connector Pin | Function |
---|---|---|
V_P, V_N | J2-113, J2-115 | System Monitor |
DX_P, DX_N | J2-119, J2-121 | Temperature-sensing diode pins |
Table 69: B2B connector pin-out of analog input pins
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MIO | Signal Name | U7 Pin | MIO | Signal Name | U17 Pin | |
---|---|---|---|---|---|---|
0 | SPI Flash CLK | B2 | 7 | SPI Flash CS | C2 | |
1 | SPI Flash IO1 | D2 | 8 | SPI Flash IO0 | D3 | |
2 | SPI Flash IO2 | C4 | 9 | SPI Flash IO1 | D2 | |
3 | SPI Flash IO3 | D4 | 10 | SPI Flash IO2 | C4 | |
4 | SPI Flash IO0 | D3 | 11 | SPI Flash IO3 | D4 | |
5 | SPI Flash CS | C2 | 12 | SPI Flash CLK | B2 |
Table 710: PS MIO pin assignment of the Quad SPI Flash memory ICs.
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PS MIO | Function | Connected to |
---|---|---|
0 | SPI0 | U7-B2, CLK |
1 | SPI0 | U7-D2, DO/IO1 |
2 | SPI0 | U7-C4, WP/IO2 |
3 | SPI0 | U7-D4, HOLD/IO3 |
4 | SPI0 | U7-D3, DI/IO0 |
5 | SPI0 | U7-C2, CS |
6 | N/A | Not connected |
7 | SPI1 | U17-C2, CS |
8 | SPI1 | U17-D3, DI/IO0 |
9 | SPI1 | U17-D2, DO/IO1 |
10 | SPI1 | U17-C4, WP/IO2 |
11 | SPI1 | U17-D4, HOLD/IO3 |
12 | SPI1 | U17-B2, CLK |
13 ..20 | eMMC | U6, MMC-D0..D7 |
33 | MIO | B2B |
34..37 | - | Not connected |
38 | I2C | U10-12, SCL |
39 | I2C | U10-19, SDA |
. 77 | user dependent | B2B connector J2 |
Table 11: TE0807-02 Table 8: TE0807-01 PS MIO mapping
The TE0808 TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.
Name | IC | Designator | PS7 | MIO | Notes | |
---|---|---|---|---|---|---|
SPI Flash | N25Q256A11E1240EN25Q512A11G1240E | U7 | QSPI0 | MIO0 ... MIO5 | dual parallel booting possible, | 3264 MByte memory per Flash IC at standard configuration |
SPI Flash | N25Q256A11E1240EN25Q512A11G1240E | U17 | QSPI0 | MIO7 ... MIO12as above |
Table 1012: Peripherals connected to the PS MIO pins.
The TE0807-01 02 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit 64bit wide data bus.
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.
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Input | Connected to | Frequency | Notes | ||||
---|---|---|---|---|---|---|---|
IN0 | On-board Oscillator (U25) | 25.000000 MHz | - | ||||
IN1 | B2B Connector pins J2-4, J2-6 (differential pair) | User | AC decoupling required on base | ||||
IN2 | B2B Connector pins J3-66, J3-68 (differential pair) | User | AC decoupling required on base | ||||
IN3 | OUT9 | User | Loop-back from OUT9 | ||||
XA/XB | Quartz (Y1) | 50.000 MHz | - | ||||
Output | Connected to | Frequency | Notes | ||||
OUT0 | B2B Connector pins J2-3, J2-1 (differential pair) | User | Default off | ||||
OUT1 | B230 B227 CLK0 | User | Default off | ||||
OUT2B229 | CLK1B226 CLK0 | User | Default off | ||||
OUT3 | B228 B225 CLK1 | User | Default off | ||||
OUT4B505 | CLK2B224 CLK1 | User | Default off | ||||
OUT5 | B505 CLK3CLK2 | User | Default off | ||||
OUT6B128 | CLK0B505 CLK3 | User | Default off | ||||
OUT7 | B2B Connector pins J2-7, J2-9 (differential pair) | User | Default off | ||||
OUT8 | B2B Connector pins J2-13, J2-15 (differential pair) | User | Default off | ||||
OUT9 | IN3 (Loop-back) | User | Default off | XA/XB | Quartz (Y1) | 50.000 MHz | - |
Table 1113: Programmable PLL clock generator input/output.
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Signal | B2B Connector Pin | Function |
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PLL_FINC | J2-81 | Frequency increment. |
PLL_LOLN | J2-85 | Loss of lock (active-low). |
PLL_SEL0 / PLL_SEL1 | J2-93 / J2-87 | Manual input switching. |
PLL_FDEC | J2-94 | Frequency decrement. |
PLL_RST | J2-5989 | Device reset (active-low) |
PLL_SCL / PLL_SDA | J2-90 / J2-92 | I2C interface, external pull-ups needed for SCL / SDA lines. I2C address in current configuration: 1101000b. |
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The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.
Clock | Signal Schematic Name | Frequency | Connected to Bank 503 Pin | Connected to|
---|---|---|---|---|
MEMS Oscillator, U32 | PS_CLK | 33.333333 MHz | Bank 503 Pin P20 | MEMS Oscillator, U32 |
PS_PAD (RTC) | 32.768 kHz | R22/R23 | Quartz crystal, Y2 | |
Quartz crystal, Y2 | XTALI / XTALO | 32.768 kHz | Bank 503 Pin R22/R23 | |
Quartz crystal, Y1 | XAXB_P / XAXB_N | 50.000 MHz | PLL U5, Pin XA/XB |
Table 13: On-board osciallators
There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I2C bus on B2B connector J2-92 (PLL_SDA) / J2-90 (PLL_SCL)Table 13: Reference clock-signals to PS configuration bank 503.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Red | DONE signal (PS Configuration Bank 503) | This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly. |
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Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The TE0808 TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
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The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.
On the TE0808-04 TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:
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See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.
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Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | B2B J4 Pins | Directions | Note |
---|---|---|---|---|---|---|
PL_DCIN | 151, 153, 157, 159 | - | - | - | Input | - |
DCDCIN | - | 154, 156, 158, 160, | - | - | Input | - |
LP_DCDC | - | 138, 140, 142, 144 | - | - | Input | - |
PS_BATT | - | 125 | - | - | Input | - |
GT_DCDC | - | - | 157, 158, 159, 160 | - | Input | - |
PLL_3V3 | - | - | 152 | - | Input | U5 (programmable PLL) 3.3V nominal input |
SI_PLL_1V8 | - | - | 151 | - | Output | Internal voltage level 1.8V nominal output |
PS_1V8 | - | 99 | 147, 148 | - | Output | Internal voltage level |
PL_1V8 | 91, 121 | - | - | - | Output | Internal voltage level |
DDR_1V2 | - | 135 | - | - | Output | Internal voltage level |
VCCO47 | - | - | 43, 44 | - | Input | - |
VCCO48 | - | - | 15, 16 | - | Input | - |
VCCO64 | - | - | - | 58, 106 | Input | - |
VCCO65 | - | - | - | 69, 105 | Input | - |
VCCO66 | 90, 120 | - | - | - | Input | - |
Table 16: TE0807-01 02 power rails
Bank | Type | Schematic Name | Voltage | Reference Input Voltage | Voltage Range |
---|---|---|---|---|---|
47 | HD | VCCO47 | user | - | 1.2V to 3.3V |
48 | HD | VCCO48 | user | - | 1.2V to 3.3V |
64 | HP | VCCO64 | user | VREF_64, pin J4-88 | 1.2V to 1.8V |
65 | HP | VCCO65 | user | VREF_65, pin J4-15 | 1.2V to 1.8V |
66 | HP | VCCO66 | user | VREF_66, pin J1-108 | 1.2V to 1.8V |
500 | MIO | PS_1V8 | 1.8V | - | - |
501 | MIO | PS_1V8 | 1.8V | - | - |
502 | MIO | PS_1V8 | 1.8V | - | - |
503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 17: TE0807-01 02 I/O bank voltages
See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.
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