Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Table 3: Selectable boot modes by dedicated boot mode pins.

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

...

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 02 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

...

BankTypeLaneSignal NameB2B PinFPGA Pin
224GTH0
  • B224_RX0_P
  • B224_RX0_N
  • B224_TX0_P
  • B224_TX0_N
  • J1-69
  • J1-71
  • J1-68
  • J1-70
  • MGTHRXP0_224, V2
  • MGTHRXN0_224, V1
  • MGTHTXP0_224, W4
  • MGTHTXN0_224, W3
1
  • B224_RX1_P
  • B224_RX1_N
  • B224_TX1_P
  • B224_TX1_N
  • J1-63
  • J1-65
  • J1-62
  • J1-64
  • MGTHRXP1_224, U4
  • MGTHRXN1_224, U3
  • MGTHTXP1_224, V6
  • MGTHTXN1_224, V5
2
  • B224_RX2_P
  • B224_RX2_N
  • B224_TX2_P
  • B224_TX2_N
  • J1-57
  • J1-59
  • J1-56
  • J1-58
  • MGTHRXP2_224, T2
  • MGTHRXN2_224, T1
  • MGTHTXP2_224, T6
  • MGTHTXN2_224, T5
3
  • B224_RX3_P
  • B224_RX3_N
  • B224_TX3_P
  • B224_TX3_N
  • J1-51
  • J1-53
  • J1-50
  • J1-52
  • MGTHRXP3_224, P2
  • MGTHRXN3_224, P1
  • MGTHTXP3_224, R4
  • MGTHTXN3_224, R3
225GTH0
  • B225_RX0_P
  • B225_RX0_N
  • B225_TX0_P
  • B225_TX0_N
  • J1-45
  • J1-47
  • J1-44
  • J1-46
  • MGTHRXP0_225, N4
  • MGTHRXN0_225, N3
  • MGTHTXP0_225, P6
  • MGTHTXN0_225, P5
1
  • B225_RX1_P
  • B225_RX1_N
  • B225_TX1_P
  • B225_TX1_N
  • J1-39
  • J1-41
  • J1-38
  • J1-40
  • MGTHRXP1_225, M2
  • MGTHRXN1_225, M1
  • MGTHTXP1_225, M6
  • MGTHTXN1_225, M5
2
  • B225_RX2_P
  • B225_RX2_N
  • B225_TX2_P
  • B225_TX2_N
  • J1-33
  • J1-35
  • J1-32
  • J1-34
  • MGTHRXP2_225, K2
  • MGTHRXN2_225, K1
  • MGTHTXP2_225, L4
  • MGTHTXN2_225, L3
3
  • B225_RX3_P
  • B225_RX3_N
  • B225_TX3_P
  • B225_TX3_N
  • J1-27
  • J1-29
  • J1-26
  • J1-28
  • MGTHRXP3_225, J4
  • MGTHRXN3_225, J3
  • MGTHTXP3_225, K6
  • MGTHTXN3_225, K5
226GTH0
  • B226_RX0_P
  • B226_RX0_N
  • B226_TX0_P
  • B226_TX0_N
  • J1-21
  • J1-23
  • J1-20
  • J1-22
  • MGTHRXP0_226, H2
  • MGTHRXN0_226, H1
  • MGTHTXP0_226, H6
  • MGTHTXN0_226, H5
1
  • B226_RX1_P
  • B226_RX1_N
  • B226_TX1_P
  • B226_TX1_N
  • J1-15
  • J1-17
  • J1-14
  • J1-16
  • MGTHRXP1_226, G4
  • MGTHRXN1_226, G3
  • MGTHTXP1_226 G8
  • MGTHTXN1_226, G7
2
  • B226_RX2_P
  • B226_RX2_N
  • B226_TX2_P
  • B226_TX2_N
  • J1-9
  • J1-11
  • J1-8
  • J1-10
  • MGTHRXP2_226, F2
  • MGTHRXN2_226, F1
  • MGTHTXP2_226, F6
  • MGTHTXN2_226, F5
3
  • B226_RX3_P
  • B226_RX3_N
  • B226_TX3_P
  • B226_TX3_N
  • J1-3
  • J1-5
  • J1-2
  • J1-4
  • MGTHRXP3_226, E4
  • MGTHRXN3_226, E3
  • MGTHTXP3_226, E8
  • MGTHTXN3_226, E7
227GTH0
  • B227_TX0_P
  • B227_TX0_N
  • B227_RX0_P
  • B227_RX0_N
  • J2-45
  • J2-43
  • J2-48
  • J2-46
  • MGTHRXP0_227, D1
  • MGTHRXN0_227, D2
  • MGTHTXP0_227, D5
  • MGTHTXN0_227, D6
1
  • B227_TX1_P
  • B227_TX1_N
  • B227_RX1_P
  • B227_RX1_N
  • J2-39
  • J2-37
  • J2-42
  • J2-40
  • MGTHRXP1_227, C3
  • MGTHRXN1_227, C4
  • MGTHTXP1_227, C7
  • MGTHTXN1_227, C8
2
  • B227_TX2_P
  • B227_TX2_N
  • B227_RX2_P
  • B227_RX2_N
  • J2-33
  • J2-31
  • J2-36
  • J2-34
  • MGTHRXP2_227, B1
  • MGTHRXN2_227, B2
  • MGTHTXP2_227, B5
  • MGTHTXN2_227, B6
3
  • B227_TX3_P
  • B227_TX3_N
  • B227_RX3_P
  • B227_RX3_N
  • J2-27
  • J2-25
  • J2-30
  • J2-28
  • MGTHRXP3_227, A3
  • MGTHRXN3_227, A4
  • MGTHTXP3_227, A7
  • MGTHTXN3_227, A8
505GTR0
  • B505_TX0_P
  • B505_TX0_N
  • B505_RX0_P
  • B505_RX0_N
  • J2-69
  • J2-67
  • J2-72
  • J2-70
  • PS_MGTRRXP0_505, M27
  • PS_MGTRRXN0_505, M28
  • PS_MGTRTXP0_505, L29
  • PS_MGTRTXN0_505, L30
1
  • B505_TX1_P
  • B505_TX1_N
  • B505_RX1_P
  • B505_RX1_N
  • J2-63
  • J2-61
  • J2-66
  • J2-64
  • PS_MGTRRXP1_505, K27
  • PS_MGTRRXN1_505, K28
  • PS_MGTRTXP1_505, J29
  • PS_MGTRTXN1_505, J30
2
  • B505_TX2_P
  • B505_TX2_N
  • B505_RX2_P
  • B505_RX2_N
  • J2-57
  • J2-55
  • J2-60
  • J2-58
  • PS_MGTRRXP2_505, J25
  • PS_MGTRRXN2_505, J26
  • PS_MGTRTXP2_505, H27
  • PS_MGTRTXN2_505, H28
3
  • B505_TX3_P
  • B505_TX3_N
  • B505_RX3_P
  • B505_RX3_N
  • J2-51
  • J2-49
  • J2-54
  • J2-52
  • PS_MGTRRXP3_505, G25
  • PS_MGTRRXN3_505, G26
  • PS_MGTRTXP3_505, G29
  • PS_MGTRTXN3_505, G30

Table 45: MGT lanes


There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board, and clock inputs are also . The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Clock signalBankSourceFPGA PinNotes
B224_CLK0_P224B2B, J3-62MGTREFCLK0P_224, R8Supplied by the carrier board
B224_CLK0_N224B2B, J3-60MGTREFCLK0N_224, R7Supplied by the carrier board
B224_CLK1_P224U5, CLK4_PMGTREFCLK1P_224, N8On-board Si5345A
B224_CLK1_N224U5, CLK4_NMGTREFCLK1N_224, N7On-board Si5345A
B225_CLK0_P225B2B, J3-67MGTREFCLK0P_225, L8Supplied by the carrier board
B225_CLK0_N225B2B, J2-65MGTREFCLK0N_225, L7Supplied by the carrier board
B225_CLK1_P225U5, CLK3_PMGTREFCLK1P_225, J8On-board Si5345A
B225_CLK1_N225U5, CLK3_NMGTREFCLK1N_225, J7On-board Si5345A
B226_CLK0_P226U5, CLK2_PMGTREFCLK0P_226, H10On-board Si5345A
B226_CLK0_N226U5, CLK2_NMGTREFCLK0N_226, H9On-board Si5345A
B226_CLK1_P226B2B, J3-61MGTREFCLK1P_226, F10Supplied by the carrier board
B226_CLK1_N226B2B, J3-59MGTREFCLK1N_226, F9Supplied by the carrier board
B227_CLK0_P227U5, CLK1_PMGTREFCLK0P_227, D10On-board Si5345A
B227_CLK0_N227U5, CLK1_NMGTREFCLK0N_227, D9On-board Si5345A
B227_CLK1_P227B2B, J2-22MGTREFCLK1P_227, B10Supplied by the carrier board
B227_CLK1_N227B2B, J2-24MGTREFCLK1N_227, B9Supplied by the carrier board
B505_CLK0_P505B2B, J2-10PS_MGTREFCLK0P_505, M23Supplied by the carrier board
B505_CLK0_N505B2B, J2-12PS_MGTREFCLK0N_505, M24Supplied by the carrier board
B505_CLK1_P505B2B, J2-16PS_MGTREFCLK1P_505, L25Supplied by the carrier board
B505_CLK1_N505B2B, J2-18PS_MGTREFCLK1N_505, L26Supplied by the carrier board
B505_CLK2_P505U5, CLK5_PPS_MGTREFCLK2P_505, K23On-board Si5345A
B505_CLK2_N505U5, CLK5_NPS_MGTREFCLK2N_505, K24On-board Si5345A
B505_CLK3_P505U5, CLK6_PPS_MGTREFCLK3P_505, H23On-board Si5345A
B505_CLK3_N505U5, CLK6_NPS_MGTREFCLK3N_505, H24On-board Si5345A

Table 56: MGT reference clock sources

...

JTAG SignalB2B Connector Pin
TCKJ2-120
TDIJ2-122
TDOJ2-124
TMSJ2-126

Table 47: B2B connector pin-out of JTAG interface.

...

SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed.
PROG_BJ2-100PL configuration reset signal.
INIT_BJ2-98PS is initialized after a power-on reset.
SRST_BJ2-96System reset.
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103

4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.

ERR_STATUS / ERR_OUTJ2-86 / J2-88

ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

PUDC_BJ2-127Pull-up during configuration (pulled-up to PL_1V8).

Table 58: B2B connector pin-out of MPSoC's PS configuration bank.

...

SignalB2B Connector PinFunction
V_P, V_NJ2-113, J2-115System Monitor
DX_P, DX_NJ2-119, J2-121Temperature-sensing diode pins

Table 69: B2B connector pin-out of analog input pins

...

MIOSignal NameU7 Pin
MIOSignal NameU17 Pin
0SPI Flash CLKB2
7SPI Flash CS
C2
1SPI Flash IO1
D2
8SPI Flash IO0
D3
2SPI Flash IO2
C4
9SPI Flash IO1
D2
3SPI Flash IO3D4
10SPI Flash IO2
C4
4SPI Flash IO0
D3
11SPI Flash IO3D4
5SPI Flash CS
C2
12SPI Flash CLK
B2

Table 710: PS MIO pin assignment of the Quad SPI Flash memory ICs.

...

PS MIOFunctionConnected to
0SPI0U7-B2, CLK
1SPI0U7-D2, DO/IO1
2SPI0U7-C4, WP/IO2
3SPI0U7-D4, HOLD/IO3
4SPI0U7-D3, DI/IO0 
5SPI0 U7-C2, CS
6N/ANot connected
7SPI1U17-C2, CS
8SPI1U17-D3, DI/IO0
9SPI1U17-D2, DO/IO1
10SPI1U17-C4, WP/IO2
11SPI1U17-D4, HOLD/IO3
12SPI1U17-B2, CLK
13 ..20eMMCU6, MMC-D0..D7
33MIOB2B
34..37-Not connected
38I2CU10-12, SCL
39I2CU10-19, SDA
. 77user dependentB2B connector J2

Table 11: TE0807-02 Table 8: TE0807-01 PS MIO mapping

On-board Peripherals

Flash

The TE0808 TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

32
 NameICDesignatorPS7MIONotes
SPI FlashN25Q256A11E1240EN25Q512A11G1240EU7QSPI0MIO0 ... MIO5dual parallel booting possible, 64 MByte memory per Flash IC at standard configuration
SPI FlashN25Q256A11E1240EN25Q512A11G1240EU17QSPI0MIO7 ... MIO12as above

Table 1012: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-01 02 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit 64bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

...

InputConnected toFrequencyNotes
IN0On-board Oscillator (U25)25.000000 MHz-
IN1B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
XA/XBQuartz (Y1)50.000 MHz-
OutputConnected toFrequencyNotes
OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault off
OUT1B230 B227 CLK0UserDefault off
OUT2B229 CLK1B226 CLK0UserDefault off
OUT3B228 B225 CLK1UserDefault off
OUT4B505 CLK2B224 CLK1UserDefault off
OUT5B505 CLK3CLK2UserDefault off
OUT6B128 CLK0B505 CLK3UserDefault off
OUT7B2B Connector pins J2-7, J2-9 (differential pair)UserDefault off
OUT8B2B Connector pins J2-13, J2-15 (differential pair)UserDefault off
OUT9IN3 (Loop-back)UserDefault offXA/XBQuartz (Y1)50.000 MHz-

Table 1113: Programmable PLL clock generator input/output.

...

SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency increment.
PLL_LOLNJ2-85Loss of lock (active-low).
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual input switching.
PLL_FDECJ2-94Frequency decrement.
PLL_RSTJ2-5989

Device reset (active-low)

PLL_SCL / PLL_SDAJ2-90 / J2-92

I2C interface, external pull-ups needed for SCL / SDA lines.

I2C address in current configuration: 1101000b.

...

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Connected to
ClockSignal Schematic NameFrequencyConnected to Bank 503 Pin
MEMS Oscillator, U32PS_CLK33.333333 MHzBank 503 Pin P20MEMS Oscillator, U32
PS_PAD (RTC)32.768 kHzR22/R23Quartz crystal, Y2
Quartz crystal, Y2XTALI / XTALO32.768 kHzBank 503 Pin R22/R23
Quartz crystal, Y1XAXB_P / XAXB_N50.000 MHzPLL U5, Pin XA/XB

Table 13: On-board osciallators

MAC Address EEPROMs

There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I2C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL)Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

LED

ColorConnected toDescription and Notes
D1RedDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

...

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808 TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

...

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-04 TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

...

Scroll Title
anchorFigure_3
titleFigure 3: TE0807-01 Power Distribution Diagram
Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision1
diagramNameTE0807 power distribution diagram
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth642

Scroll Only



See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

...

Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins

Directions

Note
PL_DCIN151, 153, 157, 159---Input-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

--Input-
LP_DCDC-138, 140, 142, 144--Input-
PS_BATT-125--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-135--Output

Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-

Table 16: TE0807-01 02 power rails

Bank Voltages

BankTypeSchematic NameVoltageReference Input VoltageVoltage Range
47HDVCCO47user-1.2V to 3.3V
48HDVCCO48user-1.2V to 3.3V
64HPVCCO64userVREF_64, pin J4-881.2V to 1.8V
65HPVCCO65userVREF_65, pin J4-151.2V to 1.8V
66HPVCCO66userVREF_66, pin J1-1081.2V to 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 17: TE0807-01 02 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

...